• Title/Summary/Keyword: Dual loop

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A 0.5-2.0 GHz Dual-Loop SAR-controlled Duty-Cycle Corrector Using a Mixed Search Algorithm

  • Han, Sangwoo;Kim, Jongsun
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.13 no.2
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    • pp.152-156
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    • 2013
  • This paper presents a fast-lock dual-loop successive approximation register-controlled duty-cycle corrector (SARDCC) circuit using a mixed (binary+sequential) search algorithm. A wider duty-cycle correction range, higher operating frequency, and higher duty-cycle correction accuracy have been achieved by utilizing the dual-loop architecture and the binary search SAR that achieves the fast duty-cycle correcting property. By transforming the binary search SAR into a sequential search counter after the first DCC lock-in, the proposed dual-loop SARDCC keeps the closed-loop characteristic and tracks variations in process, voltage, and temperature (PVT). The measured duty cycle error is less than ${\pm}0.86%$ for a wide input duty-cycle range of 15-85 % over a wide frequency range of 0.5-2.0 GHz. The proposed dual-loop SARDCC is fabricated in a 0.18-${\mu}m$, 1.8-V CMOS process and occupies an active area of $0.075mm^2$.

Optimization of Diesel Engine Performance with Dual Loop EGR considering Boost Pressure, Back Pressure, Start of Injection and Injection Mass (과급압력, 배압, 분사 시기 및 분사량에 따른 복합 방식 배기 재순환 시스템 적용 디젤 엔진의 최적화에 대한 연구)

  • Park, Jung-Soo;Lee, Kyo-Seung;Song, Soon-Ho;Chun, Kwang-Min
    • Transactions of the Korean Society of Automotive Engineers
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    • v.18 no.5
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    • pp.136-144
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    • 2010
  • Exhaust gas recirculation (EGR) is an emission control technology allowing significant NOx emission reduction from light-and heavy duty diesel engines. The future EGR type, dual loop EGR, combining features of high pressure loop EGR and low pressure loop EGR, was developed and optimized by using a commercial engine simulation program, GT-POWER. Some variables were selected to control dual loop EGR system such as VGT (Variable Geometry Turbocharger)performance, especially turbo speed, flap valve opening diameter at the exhaust tail pipe, and EGR valve opening diameter. Applying the dual loop EGR system in the light-duty diesel engine might cause some problems, such as decrease of engine performance and increase of brake specific fuel consumption (BSFC). So proper EGR rate (or mass flow) control would be needed because there are trade-offs of two types of the EGR (HPL and LPL) features. In this study, a diesel engine under dual loop EGR system was optimized by using design of experiment (DoE). Some dominant variables were determined which had effects on torque, BSFC, NOx, and EGR rate. As a result, optimization was performed to compensate the torque and BSFC by controlling start of injection (SOI), injection mass and EGR valves, etc.

New Configuration of a PLDRO with an Interconnected Dual PLL Structure for K-Band Application

  • Jeon, Yuseok;Bang, Sungil
    • Journal of electromagnetic engineering and science
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    • v.17 no.3
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    • pp.138-146
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    • 2017
  • A phase-locked dielectric resonator oscillator (PLDRO) is an essential component of millimeter-wave communication, in which phase noise is critical for satisfactory performance. The general structure of a PLDRO typically includes a dual loop of digital phase-locked loop (PLL) and analog PLL. A dual-loop PLDRO structure is generally used. The digital PLL generates an internal voltage controlled crystal oscillator (VCXO) frequency locked to an external reference frequency, and the analog PLL loop generates a DRO frequency locked to an internal VCXO frequency. A dual loop is used to ease the phase-locked frequency by using an internal VCXO. However, some of the output frequencies in each PLL structure worsen the phase noise because of the N divider ratio increase in the digital phase-locked loop integrated circuit. This study examines the design aspects of an interconnected PLL structure. In the proposed structure, the voltage tuning; which uses a varactor diode for the phase tracking of VCXO to match with the external reference) port of the VCXO in the digital PLL is controlled by one output port of the frequency divider in the analog PLL. We compare the proposed scheme with a typical PLDRO in terms of phase noise to show that the proposed structure has no performance degradation.

A Design of an Integer-N Dual-Loop Phase.Delay Locked Loop (이중루프 위상.지연고정루프 설계)

  • Choi, Young-Shig;Choi, Hyek-Hwan
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.15 no.7
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    • pp.1552-1558
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    • 2011
  • In this paper, a dual-loop Integer-N phase-delay locked loop(P DLL) architecture has been proposed using a low power consuming voltage controlled delay line(VCDL). The P DLL can have the LF of one small capacitance instead of the conventional second or third-order LF which occupies a large area. The proposed dual-loop P DLL can have a small gain VCDL by controlling the magnitude of capacitor and charge pump current on the loop of VCDL. The proposed dual-loop P DLL has been designed based on a 1.8V $0.18{\mu}m$ CMOS process and proved by Hspice simulation.

Stability Analysis and Improvement of the Capacitor Current Active Damping of the LCL Filters in Grid-Connected Applications

  • Xu, Jinming;Xie, Shaojun;Zhang, Binfeng
    • Journal of Power Electronics
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    • v.16 no.4
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    • pp.1565-1577
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    • 2016
  • For grid-connected LCL-filtered inverters, dual-loop current control with an inner-loop active damping (AD) based on capacitor current feedback is generally used for the sake of current quality. However, existing studies on capacitor current feedback AD with a control delay do not reveal the mathematical relation among the dual-loop stability, capacitor current feedback factor, delay time and LCL parameters. The robustness was not investigated through mathematical derivations. Thus, this paper aims to provide a systematic study of dual-loop current control in a digitally-controlled inverter. At first, the stable region of the inner-loop AD is derived. Then, the dual-loop stability and robustness are analyzed by mathematical derivations when the inner-loop AD is stable and unstable. Robust design principles for the inner-loop AD feedback factor and the outer-loop current controller are derived. Most importantly, ensuring the stability of the inner-loop AD is critical for achieving high robustness against a large grid impedance. Then, several improved approaches are proposed and synthesized. The limitations and benefits of all of the approaches are identified to help engineers apply capacitor current feedback AD in practice.

Design of Wide - range Clock and Data Recovery Circuit based Dual-loop DLL using 2-step DPC (2-step DPC를 이용한 이중루프 DLL기반의 광대역 클록 데이터 복원회로 설계)

  • Jung, Ki-Sang;Kim, Kang-Jik;Ko, Gui-Han;Cho, Seong-Ik
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.61 no.2
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    • pp.324-328
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    • 2012
  • A recovered jitter of CDR(Clock and Data Recovery) Circuit based on Dual-loop DLL(Delay Locked Loop) for data recovery in high speed serial data communication is changed by depending on the input data and reference clock frequency. In this paper, 2-step DPC which has constant jitter performance for wide-range input frequency is proposed. The designed prototype 2-step CDR using proposed 2-step DPC has operation frequency between 200Mbps and 4Gbps. Average delay step of 2-step DPC is 10ps. Designed CDR circuit was tested with 0.18um CMOS process.

A Wide-Range Dual-Loop DLL using VCDL with Transmission Gate Inverters (TG Inverter VCDL을 사용한 광대역 Dual-Loop DLL)

  • Lee, Seok-Ho;Kim, Sam-Dong;Hwang, In-Seok
    • Proceedings of the IEEK Conference
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    • pp.829-832
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    • 2005
  • This paper describes a wide-range dual-loop Delay Locked Loop (DLL) using Voltage Controlled Delay Line (VCDL) based on Transmission Gate(TG) inverters. One loop is used when the minimum VCDL delay is greater than a half of $T_{REF}$, the reference clock period. The other loop is initiated when the minimum delay is less than $0.5{\times}T_{REF}$. The proposed VCDL improves the dynamic operation range of a DLL. The DLL with a VCDL of 10 TG inverters provides a lock range from 70MHz to 700MHz when designed using $0.18{\mu}m$ CMOS technology with 1.8 supply voltage. The DLL consumes 11.5mW for locking operation with a 700MHz reference clock. The proposed DLL can be used for high-speed memory devices and processors, communication systems, high-performance display interfaces, etc.

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A DSP-Based Dual Loop Digital Controller Design and Implementation of a High Power Boost Converter for Hybrid Electric Vehicles Applications

  • Ellabban, Omar;Mierlo, Joeri Van;Lataire, Philippe
    • Journal of Power Electronics
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    • v.11 no.2
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    • pp.113-119
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    • 2011
  • This paper presents a DSP based direct digital control design and implementation for a high power boost converter. A single loop and dual loop voltage control are digitally implemented and compared. The real time workshop (RTW) is used for automatic real-time code generation. Experimental results of a 20 kW boost converter based on the TMS320F2808 DSP during reference voltage changes, input voltage changes, and load disturbances are presented. The results show that the dual loop control achieves better steady state and transient performance than the single loop control. In addition, the experimental results validate the effectiveness of using the RTW for automatic code generation to speed up the system implementation.

Design and Fabrication of Low Phase-Noise Frequency Synthesizer using Dual Loop PLL for IMT-2000 (이중루프 PLL을 이용한 IMT-2000용 저위상잡음 주파수합성기의 설계 및 제작)

  • 김광선;최현철
    • Proceedings of the IEEK Conference
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    • pp.163-166
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    • 1999
  • In this paper, frequency synthesizer that can be used in IMT-2000 was designed and fabricated using dual loop PLL(Phase Locked Loop). For improving phase noise characteristic Voltage Controlled Oscillator was fabricated using coaxial resonator and eliminated frequency divider using SPD as phase detector and increased open loop gain. Fabricated frequency synthesizer had 1.82㎓ center frequency, 160MHz tuning range and -119.73㏈c/Hz low phase noise characteristic.

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A Design of PLL for 6 Gbps Transmitter in Display Interface Application (디스플레이 인터페이스에 적용된 6 Gbps급 송신기용 PLL(Phase Locked Loop) 설계)

  • Yu, Byeong-Jae;Cho, Hyun-Mook
    • Journal of IKEEE
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    • v.17 no.1
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    • pp.16-21
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    • 2013
  • Recently, frequency synthesizers are being designed in two ways narrow-band loop or dual-loop for wide-band to reduce the phase noise. However, dual-loop has the disadvantage of center frequency mismatch and requiring an extra loop. In this paper, we propose a new structure that supports a range of 800Mhz ~ 3Ghz with multiple control of the single-loop frequency synthesizer without another loop. The control voltage of the VCO(coarse, fine) will be fixed, and finally the VCO will have a low Kvco. The frequency synthesizer is simulated using UMC $0.11{\mu}m$ process, proposed frequency synthesizer can be used in a variety of applications in the future.