• Title/Summary/Keyword: Silicon wafer

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A Study on Low Temperature Bonding of Si-wafer by Surface Activated Method (표면활성화법에 의한 실리콘웨이퍼의 저온접합에 관한연구)

    • Journal of the Korean Society of Manufacturing Technology Engineers
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    • v.6 no.4
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    • pp.34-38
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    • 1997
  • This paper presents a joining method by using the silicon wafer in order to apply to joint to the 3-dimensional structures of semiconductor device, high-speed , high integration, micro machine, silicon integrated sensor, and actuator. In this study, the high atomic beam, stabilized by oxidation film and organic materials at the material surface, is investigated, and the purified is obtained by removing the oxidation film and pollution layer at the materials. And the unstable surface is obtained, which can be easily joined. In order to use the low temperatures for the joint method, the main subjects are obtained as follows: 1) In the case of the silicon wafer and the silicon wafer and the silicon wafer of alumina sputter film, the specimens can be jointed at 2$0^{\circ}C$, and the joining strength is 5Mpa. 2) The specimens can not always be joined at the room temperatures in the case of the silicon wafer and the silicon wafer of alumina sputter film.

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Double treated mixed acidic solution texture for crystalline silicon solar cells

  • Kim, S.C.;Kim, S.Y.;Yi, J.S.
    • Proceedings of the Korean Vacuum Society Conference
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    • pp.323-323
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    • 2010
  • Saw damage of crystalline silicon wafer is unavoidable factor. Usually, alkali treatment for removing the damage has been carried out as the saw damage removal (SDR) process for priming the alkali texture. It usually takes lots of time and energy to remove the sawed damages for solar grade crystalline silicon wafers We implemented two different mixed acidic solution treatments to obtain the improved surface structure of silicon wafer without much sacrifice of the silicon wafer thickness. At the first step, the silicon wafer was dipped into the mixed acidic solution of $HF:HNO_3$=1:2 ration for polished surface and at the second step, it was dipped into the diluted mixed acidic solution of $HF:HNO_3:H_2O$=7:3:10 ratio for porous structure. This double treatment to the silicon wafer brought lower reflectance (25% to 6%) and longer carrier lifetime ($0.15\;{\mu}s$ to $0.39\;{\mu}s$) comparing to the bare poly-crystalline silicon wafer. With optimizing the concentration ratio and the dilution ratio, we can not only effectively substitute the time consuming process of SDR to some extent but also skip plasma enhanced chemical vapor deposition (PECVD) process. Moreover, to conduct alkali texture for pyramidal structure on silicon wafer surface, we can use only nitric acid rich solution of the mixed acidic solution treatment instead of implementing SDR.

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A Study on the Contaminants Precision Cleaning of Etched Silicon Wafer by Ozone/UV (오존/자외선에 의한 실리콘 웨이퍼의 정밀세정에 관한 연구)

  • Park, H.M.;Lee, C.H.;Chun, B.J.;Yoon, B.H.;Lim, C.H.;Song, H.J.;Kim, Y.H.;Lee, K.S.
    • Proceedings of the KIEE Conference
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    • pp.1820-1822
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    • 2004
  • In this study, major research fields are classified as ozone generation system for dry cleaning wafer of etched silicon wafer, dry cleaning process of etched silicon wafer which includes SEM analysis and ESCA analysis. The following results are deduced from each experiment and analysis. The magnitudes of carbon and silicon were similar to the survey spectrum of silicon wafer which does not cleaning, but magnitude of oxygen was much bigger Because UV light activates oxygen molecules in the oxide film on the silicon wafer.

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Realization of High Q Inductor on Low Resistivity Silicon Wafer using a New and simple Trench Technique (새로운 트랜치 방법을 이용한 저저항 실리콘 기판에서의 High Q 인덕터의 구현)

  • 이홍수;이진효유현규김대용
    • Proceedings of the IEEK Conference
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    • pp.629-632
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    • 1998
  • This paper presents a new and simple technique to realize high Q inductor on low resistivity silicon wafer with 6 $\Omega$.cm. This technique is very compatible with bipolar and CMOS standard silicon process. By forming the deep and narrow trenches on the low resistivity wafer substrate under inductor pattern, oxidizing and filling with undoped polysilicon, the low resistivity silicon wafer acts as high resistivity wafer being suitable for the fabrication of high Q inductor. By using this technique the quality factor (Q) for 8-turn spiral inductor was improved up to max. 10.3 at 2 ㎓ with 3.0 $\mu\textrm{m}$ of metal thickness. The experiment results show that Q on low resistivity silicon wafer with the trench technique have been improved more than 2 times compared to the conventional low resistivity silicon wafer without trenches.

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The Study on the Denuded Zone Formation of Czochralski-grown Single Crystal Silicon Wafer (I) (Czochralski 법으로 성장시킨 단결정 Silicon Wafer에서의 표면 무결함층(Denuded Zone) 형성에 관한 연구(I))

  • 김승현;양두영;김창은;이홍림
    • Journal of the Korean Ceramic Society
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    • v.28 no.6
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    • pp.495-501
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    • 1991
  • This study is intended to make defect-free region, denuded zone at the silicon wafer surface for semiconductor device substrates. In this experiment, initial oxygen concentration of starting material CZ-grown silicon wafer, various heat treatment combinations, denuding ambient and the amounts of oxygen reduction were measured, and then denuded zone (DZ) formation and depth were investigated. In Low/High anneal (DZ formation could be achieved), the optimum temperature for Low anneal was 700$^{\circ}C$∼750$^{\circ}C$. In case of High anneal, with the time increased, DZ depth was increased at 1000$^{\circ}C$, 1150$^{\circ}C$ respectively, but on the contrary, DZ depth was decreased at low temperature 900$^{\circ}C$. As well, out-diffusion time below 2 hours was unsuitable for effective Gettering technique even though the temperature was high, and DZ formation could be achieved when initial oxygen concentration was only above 14 ppm in silicon wafer.

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Precision Measurement of Silicon Wafer Resistivity Using Single-Configuration Four-Point Probe Method (Single-configuration FPP method에 의한 실리콘 웨이퍼의 비저항 정밀측정)

  • Kang, Jeon-Hong;Yu, Kwang-Min;Koo, Kung-Wan;Han, Sang-Ok
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.60 no.7
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    • pp.1434-1437
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    • 2011
  • Precision measurement of silicon wafer resistivity has been using single-configuration Four-Point Probe(FPP) method. This FPP method have to applying sample size, shape and thickness correction factor for a probe pin spacing to precision measurement of silicon wafer. The deference for resistivity measurement values applied correction factor and not applied correction factor was about 1.0 % deviation. The sample size, shape and thickness correction factor for a probe pin spacing have an effects on precision measurement for resistivity of silicon wafer.

The Behavior of Intrinsic Bubbles in Silicon Wafer Direct Bonding (실리콘 웨이퍼 직접접합에서 내인성 Bubble의 거동에 관한 연구)

  • Moon, Do-Min;Jeong, Hae-Do
    • Journal of the Korean Society for Precision Engineering
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    • v.16 no.3
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    • pp.78-83
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    • 1999
  • The bonding interface is dependent on the properties of surfaces prior to SDB(silicon wafer direct bonding). In this paper, we prepared silicon surfaces in several chemical solutions, and annealed bonding wafers which were combined with thermally oxidized wafers and bare silicon wafers in the temperature range of $600{\times}1000^{\circ}C$. After bonding, the bonding interface is investigated by an infrared(IR) topography system which uses the penetrability of infrared through silicon wafer. Using this procedure, we observed intrinsic bubbles at elevated temperatures. So, we verified that these bubbles are related to cleaning and drying conditions, and the interface oxides on silicon wafer reduce the formation of intrinsic bubbles.

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Monitering System of Silicon Wafer Grinding Process Using for the Change of Motor Current (모터 전류 변화를 이용한 실리콘 웨이퍼 연삭 공정 모니터링 시스템)

  • Park S.J.;Kim S.Y.;Lee S.J.;Park B.Y.;Jeong H.D.
    • Proceedings of the Korean Society of Precision Engineering Conference
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    • pp.104-107
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    • 2005
  • Recently, according to the development of semiconductor industry, needed to high-integration and high-functionality. These changes are required for silicon wafer of large scale diameter and precision of TTV (Total Thickness variation). So, in this research, suggest that the method of monitoring system is using motor current. This method is needed for observation of silicon wafer grinding process. Motor current sensor is consisted of hall sensor. Hall sensor is known to catching of change of current. Received original signal is converted to the diginal, then, it is calculated RMS values, and then, it is analysed in computer. Generally, the change of force is relative to the change of current, So this reason, in this research tried to monitoring of motor current change, and then, it will be applied to analysis for silicon wafer grinding process. using motor current sensor.

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Measurement of Oxygen by FTIR in Silicon wafer process steps (실리콘 웨이퍼 공정스텝에서 FTIR에 의한 산소의 측정)

  • 김동수;정원채
    • Proceedings of the IEEK Conference
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    • pp.68-71
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    • 2000
  • In this paper, we have measured the oxygen contents by FTIR in silicon wafer various process technology(slicing, lapping, polishing). The measured data are also compared with the data of etching process(KOH, Bright etching). Also we have measured the surface morpology in backside silicon wafer after etching treatment and etch pit density due to OISF after 4 step high temperature annealing process with optical microscope.

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Effects of Oxide Layer Formed on TiN Coated Silicon Wafer on the Friction and Wear Characteristics in Sliding (미끄럼운동 시 TiN 코팅에 형성되는 산화막이 마찰 및 마멸 특성에 미치는 영향)

  • 조정우;이영제
    • Tribology and Lubricants
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    • v.18 no.4
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    • pp.260-266
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    • 2002
  • In this study, the effects of oxide layer farmed on the wear tracks of TiN coated silicon wafer on friction and wear characteristics were investigated. Silicon wafer was used for the substrate of coated disk specimens, which were prepared by depositing TiN coating with 1 ${\mu}{\textrm}{m}$ in coating thickness. AISI 52100 steel ball was used fur the counterpart. The tests were performed both in air for forming oxide layer on the wear track and in nitrogen to avoid oxidation. This paper reports characterization of the oxide layer effects on friction and wear characteristics using X-ray diffraction(XRD), Auger electron spectroscopy(AES), scanning electron microscopy (SEM) and multi-mode atomic force microscope(AFM).