Journal of Korea Society of Digital Industry and Information Management (디지털산업정보학회논문지)

Korea Society of Digital Industry and Information Management (디지털산업정보학회)
권호 표지

Hypergraph Partitioning By Using Reodered Simulated-anealing

정련법을 이용한 하이퍼그래프 분할

  • 김상진 (경운대학교 컴퓨터공학과) ;
  • 류명춘 (경운대학교 컴퓨터공학과) ;
  • 정영석 (경운대학교 컴퓨터공학과)
  • Received : 2013.10.08
  • Accepted : 2013.11.12
  • Published : 2013.12.30
⟨ Previous Next ⟩

Abstract

In this paper we present a reodered simulated-anealing algorithm which is capable of applying odering based k-way partitioned clusters. This method is used for improvement of the objectives of partitioning which are k-way partitioned by using odering algorithm. It changes the positions of the clusters and the vertices in each clusters. Reodered vertices are splitted by using DP-RP method and this process has an opportunity to improve the objective functions. This algorithm has advantages to improve the quality of the solutions for various purposes. Experimental results on several graphs demonstrate that proposed algorithm provides substantial enhancement.

Keywords

References

  1. S. Dutt and W. Deng. "Probability-Based Approaches to VLSI Curcuit Partitioning, " IEEE Trans. CAD, Vol. 19, No. 5, May 2000, pp. 534-549 https://doi.org/10.1109/43.845078
  2. H. Nagamochi and T. Ibaraki. "Computing Edge-Connectivity in Multigraphs and Capacitated Graphs," Siam Journal of Discrete Mathematics, 5(1):54-66, 1992. https://doi.org/10.1137/0405004
  3. C. J. Alpert and A. B. Kahng. "A General Framework for Vertex Orderings, With Application to Circuit Clustering," IEEE Transactions on VLSI Systems, 4(2):240-246, June 1996. https://doi.org/10.1109/92.502195
  4. C. J. Alpert and A. B. Kahng. "Multi-Way Partitioning Via Space-filling Curves and Dynamic Programming," In Proc. of the ACM/IEEE Design Automation Conf., 1994, pp. 652-657.
  5. C. J. Alpert., "Multi-way Graph and Hypergraph Partitioning," Ph. D thesis, Dep't of Computer Science, UCLA, 1996.
  6. Y. C. Wei and C. K. Cheng. "Towards Efficient Hierarchical Designs by Ratio Cut Partitioning," In Proc. of the IEEE/ACM International Conf. on Computer-Aided Design, 1989, pp. 298-301.
  7. P. K. Chan, M. D. F. Schlag, and J. Y. Zien. "Spectral K-way Ratio-Cut Partitioning and Clustering," IEEE Transactions on Computer- Aided Design, 13(8):1088-1096, 1994. https://doi.org/10.1109/43.310898
  8. C. W. Yeh, C. K. Cheng, and T. T. Y. Lin. "A Probabilistic Multi-Commodity Flow Solution to Circuit Clustering Problems," In Proc. of the IEEE/ACM International Conf. on Computer- Aided Design, 1992, pp. 428-431.
  9. W. Son and C. Sechen. "Efficient and Effective Placements for Very Large Circuits," In Proc. of the IEEE/ACM International Conf. on Computer-Aided Design, 1993, pp. 170-177.
  10. J. Cong, L. Hagen, and A. B. Kahng. "Net Partitions Yield Better Module Partitions," In Proc. of the ACM/IEEE Design Automation Conf., 1992, pp. 47-52.
  11. D. J. H. Huang and A. B. Kahng. "When Clusters Meet Partitions: New Density-Based Methods for Circuit Decomposition," In Proc. European Design and Test Conf., March 1995, pp. 60-64,
  12. R. Rajaraman and D. F. Wong. "Optimal clustering for delay minimization," In Proc. of the ACM/IEEE Design Automation Conf., 1993, pp. 309-314.
  13. N. Selvakkumaran and G. Karypis. "Multi-Objective Hypergraph Partitioning Algorithms for Cut and Maximum Subdomain Degree Minimization," IEEE Transactions on CAD, 25(3), 2006, pp. 504-517. https://doi.org/10.1109/TCAD.2005.854637
  14. 김재진, "제한조건을 고려한 효율적 회로 설계 알고리즘," 디지털산업정보학회 논문집, 제8권, 제1호, 2012, pp. 41-46.
  15. S. J. Kim. "Reordering Algorighm for Hypergraph Partitioning," PhD thesis, Kyungpook National University, 2000.
  16. 최현준, 장석우, "FPGA를 이용한 대지털 계측 시스템의 설계 및 구현," 디지털산업정보학회 논문집, 제9권, 제2호, 2013, pp. 55-61.