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CAWR: Buffer Replacement with Channel-Aware Write Reordering Mechanism for SSDs

  • Wang, Ronghui (School of Computer, National University of Defense Technology) ;
  • Chen, Zhiguang (School of Computer, National University of Defense Technology) ;
  • Xiao, Nong (School of Computer, National University of Defense Technology) ;
  • Zhang, Minxuan (School of Computer, National University of Defense Technology) ;
  • Dong, Weihua (Department of Software, the State Key Laboratory of Astronautic Dynamics)
  • Received : 2014.01.13
  • Accepted : 2014.06.16
  • Published : 2015.02.01

Abstract

A typical solid-state drive contains several independent channels that can be operated in parallel. To exploit this channel-level parallelism, a variety of works proposed to split consecutive write sequences into small segments and schedule them to different channels. This scheme exploits the parallelism but breaks the spatial locality of write traffic; thus, it is able to significantly degrade the efficiency of garbage collection. This paper proposes a channel-aware write reordering (CAWR) mechanism to schedule write requests to different channels more intelligently. The novel mechanism encapsulates correlated pages into a cluster beforehand. All pages belonging to a cluster are scheduled to the same channels to exploit spatial locality, while different clusters are scheduled to different channels to exploit the parallelism. As CAWR covers both garbage collection and I/O performance, it outperforms existing schemes significantly. Trace-driven simulation results demonstrate that the CAWR mechanism reduces the average response time by 26% on average and decreases the valid page copies by 10% on average, while achieving a similar hit ratio to that of existing mechanisms.

Keywords

References

  1. L.-P. Chang, Y.-H. Huang, and C.-Y. Wen, "On the Management of Multichannel Architectures of Solid-State Disks," IEEE Symp. Embedded Syst. Real-Time Multimedia, Taipei, Taiwan, Oct. 13-14, 2011, pp. 37-45.
  2. S.K. Park et al., "CAVE: Channel-Aware Buffer Management Scheme for Solid State Disk," ACM Symp. Appl. Comput., Taichung, Taiwan, Mar. 21-25, 2011, pp. 346-353.
  3. A. Gupta, Y. Kim, and B. Urgaonkar, "DFTL: A Flash Translation Layer Employing Demand-Based Selective Caching of Page- Level Address Mappings," ACM Int. Conf. Archit. Support Programming Languages Operating Syst., Washington, DC, USA, Mar. 7-11, 2009, pp. 229-240.
  4. Y. Hu et al., "Achieving Page-Mapping FTL Performance at Block-Mapping FTL Cost by Hiding Address Translation," IEEE Symp. Mass Storage Syst. Technol., Incline Village, NV, USA, May 3-7, 2010, pp. 1-12.
  5. H. Jo et al., "FAB: Flash-Aware Buffer Management Policy for Portable Media Players," IEEE Trans. Consum. Electron., vol. 52, no. 2 , May 2006, pp. 485-493. https://doi.org/10.1109/TCE.2006.1649669
  6. H. Kim and S. Ahn, "BPLRU: A Buffer Management Scheme for Improving Random Writes in Flash Storage," USENIX Conf. File Storage Technol., San Jose, CA, USA, Feb. 26-29, 2008, pp. 239-252.
  7. S. Kang et al., "Performance Trade-Offs in Using NVRAM Write Buffer for Flash Memory-Based Storage Devices," IEEE Trans. Comput., vol. 58, no. 6, June 2009, pp. 744-758. https://doi.org/10.1109/TC.2008.224
  8. S.-Y. Park et al., "CFLRU: A Replacement Algorithm for Flash Memory," IEEE Int. Conf. Compilers Archit. Synthesis Embeded Syst., Seoul, Rep. of Korea, Oct. 23-25, 2006, pp. 234-241.
  9. H. Jung et al., "LRU-WSR: Integration of LRU and Writes Sequence Reordering for Flash Memory," IEEE Trans. Consum. Electron., vol. 54, no. 3, Aug. 2008, pp. 1215-1223. https://doi.org/10.1109/TCE.2008.4637609
  10. Z. Li et al., "CCF-LRU: A New Buffer Replacement Algorithm for Flash Memory," IEEE Trans. Consum. Electron., vol. 55, no. 3, Aug. 2009, pp. 1351-1359. https://doi.org/10.1109/TCE.2009.5277999
  11. D. Seo and D. Shin, "Recently-Evicted-First Buffer Replacement Policy for Flash Storage Devices," IEEE Trans. Consum. Electron., vol. 54, no. 3, Aug. 2008, pp. 1228-1235. https://doi.org/10.1109/TCE.2008.4637611
  12. Y. Kim et al., "FlashSim: A Simulator for NAND Flash-Based Solid-State Drives," Int. Conf. Adv. Syst. Simulation, Porto, Portugal, Sept. 20-25, 2009, pp. 125-131.
  13. A. Birrell et al., "A Design for High-Performance Flash Disks," Microsoft Research, Silicon Valley, CA, USA, Tech. Rep. MSRTR- 2005-176, Dec. 2005.
  14. SPC, Storage Traces form Storage Performance Council, SPC, 2009. Accessed May 22, 2013. http://traces.cs.umass.edu/
  15. SNIA, Block Traces from SNIA IOTTA Repository, SNIA, 2009. Accessed May 22, 2013. http://iotta.snia.org/traces/list/BlockIO
  16. D. Narayanan, A. Donnelly, and A. Rowstron, "Write Off- Loading: Practical Power Management for Enterprise Storage," USENIX Conf. File Storage Technol., San Jose, CA, Feb. 26-29, 2008, pp. 253-267.

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