ETRI Journal

Electronics and Telecommunications Research Institute (한국전자통신연구원)
권호 표지
DOI QR코드

DOI QR Code

5.2 mW 61 dB SNDR 15 MHz Bandwidth CT ΔΣ Modulator Using Single Operational Amplifier and Single Feedback DAC

  • Received : 2015.07.13
  • Accepted : 2015.10.29
  • Published : 2016.04.01
Download PDF
⟨ Previous Next ⟩

Abstract

We propose an architecture that reduces the power consumption and active area of such a modulator through a reduction in the number of active components and a simplification of the topology. The proposed architecture reduces the power consumption and active area by reducing the number of active components and simplifying the modulator topology. A novel second-order loop filter that uses a single operational amplifier resonator reduces the number of active elements and enhances the controllability of the transfer function. A trapezoidal-shape half-delayed return-to-zero feedback DAC eliminates the loop-delay compensation circuitry and improves pulse-delay sensitivity. These simple features of the modulator allow higher frequency operation and more design flexibility. Implemented in a 130 nm CMOS technology, the prototype modulator occupies an active area of $0.098mm^2$ and consumes 5.23 mW power from a 1.2 V supply. It achieves a dynamic range of 62 dB and a peak SNDR of 60.95 dB over a 15 MHz signal bandwidth with a sampling frequency of 780 MHz. The figure-of-merit of the modulator is 191 fJ/conversion-step.

Keywords

References

  1. G. Mitteregger et al., "A 20-mW 640-MHz CMOS Continuous-Time ${\Delta}{\Sigma}$ ADC with 20-MHz Signal Bandwidth, 80-dB Dynamic Range and 12-bit ENOB," IEEE J. Solid-State Circuits, vol. 41, no. 12, Dec. 2006, pp. 2641-2649. https://doi.org/10.1109/JSSC.2006.884332
  2. Y. Seo et al., "3-Level Envelope Delta-Sigma Modulation RF Signal Generator for High-Efficiency Transmitters," ETRI J., vol. 36, no. 6, Dec. 2014, pp. 924-930. https://doi.org/10.4218/etrij.14.0114.0176
  3. K. Matsukawa et al., "A Fifth-Order Continuous-Time Delta-Sigma Modulator with Single-Opamp Resonator," IEEE J. Solid-State Circuits, vol. 45, no. 4, Apr. 2010, pp. 697-706. https://doi.org/10.1109/JSSC.2010.2042244
  4. V. Singh et al., "A 16 MHz BW 75 dB DR CT ${\Delta}{\Sigma}$ ADC Compensated for More than One Cycle Excess Loop Delay," IEEE J. Solid-State Circuits, vol. 47, no. 8, Aug. 2012, pp. 1884-1895. https://doi.org/10.1109/JSSC.2012.2196730
  5. A. Jain, M. Venkatesan, and S. Pavan, "Analysis and Design of a High Speed Continuous-Time ${\Delta}{\Sigma}$ Modulator Using the Assisted Opamp Technique," IEEE J. Solid-State Circuits, vol. 47, no. 7, July 2012, pp. 1615-1625. https://doi.org/10.1109/JSSC.2012.2191210
  6. P. Crombez et al., "A Single Bit 6.8 mW 10 MHz Power-Optimized Continuous-Time ${\Delta}{\Sigma}$ with 67 dB DR in 90 nm CMOS," Proc. European Solid-State Circuits Conf., Athens, Greece, Sept. 14-18, 2009, pp. 336-339.
  7. V. Srinivasan et al., "A 20 mW 61 dB SNDR (60 MHz BW) 1b 3rd-Order Continuous-Time Delta-Sigma Modulator Clocked at 6 GHz in 45 nm CMOS," IEEE Int. Solid-State Circuits Conf. Dig. Techn. Papers, San Francisco, CA, USA, Feb. 19-23, 2012, pp. 158-160.
  8. E. Prefasi et al., "A $0.1mm^2$, Wide Bandwidth Continuous-Time ${\Sigma}{\Delta}$ ADC Based on a Time Encoding Quantizer in $0.13{\mu}m$ CMOS," IEEE J. Solid-State Circuits, vol. 44, no. 10, Oct. 2009, pp. 2745-2754. https://doi.org/10.1109/JSSC.2009.2027550
  9. J.-P. Petit, Digital Transmission System with a Double Analog Integrator Delta Sigma Coder and a Double Digital Integrator Delta Sigma Decoder, US patent 4,301,446, July 17, 1980, Nov. 17, 1981.
  10. R. Zanbaghi, P.K. Hanumolu, and T.S. Fiez, "An 80-dB DR, 7.2-MHz Bandwidth Single Opamp Biquad Based CT ${\Delta}{\Sigma}$ Modulator Dissipating 13.7-mW," IEEE J. Solid-State Circuits, vol. 48, no. 2, Feb. 2013, pp. 487-501. https://doi.org/10.1109/JSSC.2012.2221194
  11. C.-H. Weng et al., "An 8.5 MHz 67.2 dB SNDR CTDSM with ELD Compensation Embedded Twin-T SAB and Circular TDC-Based Quantizer in 90 nm CMOS," Symp. VLSI Circuits, Dig. Techn. Papers., Honolulu, HI, USA, June 10-13, 2014, pp. 1-2.
  12. H.-C. Tsai et al., "A 64-fJ/Conv.-Step Continuous-Time ${\Sigma}{\Delta}$ Modulator in 40-nm CMOS Using Asynchronous SAR Quantizer and Digital ${\Delta}{\Sigma}$ Truncator," IEEE J. Solid-State Circuits, vol. 48, no. 11, Nov. 2013, pp. 2637-2648. https://doi.org/10.1109/JSSC.2013.2274852
  13. R.H.M. van Veldhoven et al., "A 3.3-mW ${\Sigma}{\Delta}$ Modulator for UMTS in $0.18-{\mu}m$ CMOS with 70-dB Dynamic Range in 2-MHz Bandwidth," IEEE J. Solid-State Circuits, vol. 37, no. 12, Dec. 2002, pp. 1645-1652. https://doi.org/10.1109/JSSC.2002.804329
  14. J.A. Cherry and W.M. Snelgrove, "Continuous-Time Delta-Sigma Modulators for High-Speed A/D Conversion," Boston, MA, USA: Kluwer, 2000.
  15. K. Nguyen et al., "A 106-dB SNR Hybrid Oversampling Analog-to-Digital Converter for Digital Audio," IEEE J. Solid-State Circuits, vol. 40, no. 12, Dec. 2005, pp. 2408-2415. https://doi.org/10.1109/JSSC.2005.856284
  16. K.-P. Pun, S. Chatterjee, and P.R. Kinget, "A 0.5-V 74-dB SNDR 25-kHz Continuous-Time Delta-Sigma Modulator with a Return-to-Open DAC," IEEE J. Solid-State Circuits, vol. 42, no. 3, Mar. 2007, pp. 496-507. https://doi.org/10.1109/JSSC.2006.891716
  17. C. Kim, S. Lee, and S. Choi, "A 900 MHz Zero-IF RF Transceiver for IEEE 802.15.4g SUN OFDM Systems," ETRI J., vol. 36, no. 3, June 2014, pp. 352-360. https://doi.org/10.4218/etrij.14.0113.0549
  18. Y.-K. Cho and B.H. Park, "Single Opamp Second-Order Loop Filter for Continuous-Time Delta-Sigma Modulators," Electron. Lett., vol. 51, no. 8, Apr. 2015, pp. 619-621. https://doi.org/10.1049/el.2014.4472
  19. S. Yan and E. Sanchez-Sinencio, "A Continuous-Time ${\Sigma}{\Delta}$ Modulator with 88-dB Dynamic Range and 1.1-MHz Signal Bandwidth," IEEE J. Solid-State Circuits, vol. 39, no. 1, Jan. 2004, pp. 75-86. https://doi.org/10.1109/JSSC.2003.820856
  20. B. Kumar and J. Silva-Martinez, "A Robust Feedforward Compensation Scheme for Multistage Operational Transconductance Amplifiers with No Miller Capacitors," IEEE J. Solid-State Circuits, vol. 38, no. 2, Feb. 2003, pp. 237-243. https://doi.org/10.1109/JSSC.2002.807410
  21. Y.-K. Cho et al., "A 9-bit 80 MS/s Successive Approximation Register Analog-to-Digital Converter with a Capacitor Reduction Technique," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 57, no. 7, July 2010, pp. 502-506. https://doi.org/10.1109/TCSII.2010.2048387
  22. M. Anderson and L. Sundstrom, "Design and Measurement of a CT ${\Delta}{\Sigma}$ ADC with Switched-Capacitor Switched-Resistor Feedback," IEEE J. Solid-State Circuits, vol. 44, no. 2, Feb. 2009, pp. 473-483. https://doi.org/10.1109/JSSC.2008.2010978

Cited by

  1. Wideband and multiband long-term evolution transmitter using envelope delta-sigma modulation technique vol.91, pp.1, 2016, https://doi.org/10.1007/s10470-017-0926-2