한국정보전자통신기술학회논문지 (The Journal of Korea Institute of Information, Electronics, and Communication Technology)

  • 제10권6호
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  • Pages.558-569
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  • 2017
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  • 2005-081X(pISSN)
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  • 2288-9302(eISSN)
한국정보전자통신기술학회 (Korea Information Electronic Communication Technology)
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배터리 응용을 위한 1.5V 단일전원 256Kb EEPROM IP 설계

Design of 256Kb EEPROM IP Aimed at Battery Applications

  • Kim, Young-Hee (Department of Electronic Engineering, Changwon National University) ;
  • Jin, RiJun (Department of Electronic Engineering, Changwon National University) ;
  • Ha, Pan-Bong (Department of Electronic Engineering, Changwon National University)
  • 투고 : 2017.11.23
  • 심사 : 2017.12.21
  • 발행 : 2017.12.30
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초록

본 논문에서는 MCU 내장형 1.5V 단일전원 256Kb EEPROM IP는 배터리 응용을 위해 설계되었다. 기존의 body-potential 바이어싱 회로를 사용하는 cross-coupled VPP (Boosted Voltage) 전하펌프회로는 erase와 program 모드에서 빠져나올 때 5V cross-coupled PMOS 소자에 8.53V의 고전압이 걸리면서 junction breakdown이나 gate oxide breakdown에 의해 소자가 파괴될 수 있다. 그래서 본 논문에서는 cross-coupled 전하펌프회로의 출력 노드는 VDD로 프리차징시키는 동시에 펌핑 노드들을 각 펌핑 단의 입력전압으로 프리차징하므로 5V PMOS 소자에 5.5V 이상의 고전압이 걸리지 않도록 하므로 breakdown이 일어나는 것을 방지하였다. 한편 256Kb을 erase하거나 program하는 시간을 줄이기 위해 all erase, even program, odd program과 all program 모드를 지원하고 있다. 또한 cell disturb 테스트 시간을 줄이기 위해 cell disturb 테스트 모드를 이용하여 256Kb EEPROM 셀의 disturb를 한꺼번에 인가하므로 disturb 테스트 시간을 줄였다. 마지막으로 이 논문에서는 erase-verify-read 모드에서 40ns의 cycle 시간을 만족하기 위해 CG disable 시간이 빠른 CG 구동회로는 새롭게 제안되었다.

In this paper, a 256Kb EEPROM IP aimed at battery applications using a single supply of 1.5V which is embedded into an MCU is designed. In the conventional cross-coupled VPP (boosted voltage) charge pump using a body-potential biasing circuit, cross-coupled PMOS devices of 5V in it can be broken by the junction or gate oxide breakdown due to a high voltage of 8.53V applied to them in exiting the program or erase mode. Since each pumping node is precharged to the input voltage of the pumping stage at the same time that the output node is precharged to VDD in the cross-coupled charge pump, a high voltage of above 5.5V is prevented from being applied to them and thus the breakdown does not occur. Also, all erase, even program, odd program, and all program modes are supported to reduce the times of erasing and programming 256 kilo bits of cells. Furthermore, disturbance test time is also reduced since disturbance is applied to all the 256 kilo bits of EEPROM cells at once in the cell disturb test modes to reduce the cell disturbance testing time. Lastly, a CG driver with a short disable time to meet the cycle time of 40ns in the erase-verify-read mode is newly proposed.

키워드

참고문헌

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