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Electronics and Telecommunications Research Institute (한국전자통신연구원)
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High speed wide fan-in designs using clock controlled dual keeper domino logic circuits

  • Angeline, A. Anita (School of Electronics Engineering, VIT University) ;
  • Bhaaskaran, V.S. Kanchana (School of Electronics Engineering, VIT University)
  • Received : 2018.06.12
  • Accepted : 2018.10.08
  • Published : 2019.06.03
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Abstract

Clock Controlled Dual keeper Domino logic structures (CCDD_1 and CCDD_2) for achieving a high-speed performance with low power consumption and a good noise margin are proposed in this paper. The keeper control circuit comprises an additional PMOS keeper transistor controlled by the clock and foot node voltage. This control mechanism offers abrupt conditional control of the keeper circuit and reduces the contention current, leading to high-speed performance. The keeper transistor arrangement also reduces the loop gain associated with the feedback circuitry. Hence, the circuits offer less delay variability. The design and simulation of various wide fan-in designs using 180 nm CMOS technology validates the proposed CCDD_1 and CCDD_2 designs, offering an increased speed performance of 7.2% and 8.5%, respectively, over a conventional domino logic structure. The noise gain margin analysis proves good robustness of the CCDD structures when compared with a conventional domino logic circuit configuration. A Monte Carlo simulation for 2,000 runs under statistical process variations demonstrates that the proposed CCDD circuits offer a significantly reduced delay variability factor.

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References

  1. L. Ding and P. Mazumder, On circuit techniques to improve noise immunity of CMOS dynamic logic, IEEE Trans. Very Large Scale Integr. Syst. 12 (2004), no. 9, 910-925. https://doi.org/10.1109/TVLSI.2004.833668
  2. B. Chatterjee, M. Sachdev, and R. Krishnamurthy, Leakage control techniques for designing robust, low power wide‐OR domino logic for sub‐130nm CMOS technologies, in Proc. Int. Symp. InQuality Electron. Design, San Jose, CA, USA, Mar. 2004, pp. 415-420.
  3. F. Moradi et al., Domino logic designs for high‐performance and leakage‐tolerant applications, Integr. 46 (2013), no. 3, 247-254. https://doi.org/10.1016/j.vlsi.2012.04.005
  4. V. G. Oklobdzija and R. K. Montoye, Design‐performance trade‐offs in CMOS‐domino logic, IEEE J. Solid‐State Circuits 21 (1986), no. 2, 304-306. https://doi.org/10.1109/JSSC.1986.1052519
  5. F. Frustaci et al., High‐performance noise‐tolerant circuit techniques for CMOS dynamic logic, IET Circuits Devices Syst. 2 (2008), no. 6, 537-548. https://doi.org/10.1049/iet-cds:20080070
  6. N. Gong et al., Analysis and optimization of leakage current characteristics in sub‐65nm dual Vt footed domino circuits, Microelectron. J. 39 (2008), no. 9, 1149-1155. https://doi.org/10.1016/j.mejo.2008.01.028
  7. S. Garg and T. K. Gupta, Low power domino logic circuits in deep‐submicron technology using CMOS, Eng. Sci. Technol. Int. J. 21 (2018), 625-638. https://doi.org/10.1016/j.jestch.2018.06.013
  8. M. H. Anis, M. W. Allam, and M. I. Elmasry, Energy‐efficient noise‐tolerant dynamic styles for scaled‐down CMOS and MTCMOS technologies, IEEE Trans. Very Large Scale Integr. Syst. 10 (2002), no. 2, 71-78. https://doi.org/10.1109/92.994977
  9. S. M. Sharroush et al., Speeding‐up wide‐fan in domino logic using a controlled strong PMOS keeper, in Int. Conf. Comput. Commun. Eng., Kuala Lumpur, Malaysia, May 2008, pp. 633-637.
  10. A. Alvandpour et al., A sub‐130‐nm conditional keeper technique, IEEE J. Solid‐State Circuits 37 (2002), no. 5, 633-638. https://doi.org/10.1109/4.997857
  11. Y. Lih, N. Tzartzanis, and W. W. Walker, A leakage current replica keeper for dynamic circuits, IEEE J. Solid‐State Circuits 42 (2007), no. 1, 48-55. https://doi.org/10.1109/JSSC.2006.885051
  12. G. Palumbo, M. Pennisi, and M. Alioto, A simple circuit approach to reduce delay variations in domino logic gates, IEEE Trans. Circuits Syst. I: Regular Papers 59 (2012), no. 10, 2292-2300. https://doi.org/10.1109/TCSI.2012.2189046
  13. H. F. Dadgour and K. Banerjee, A novel variation‐tolerant keeper architecture for high‐performance low‐power wide fan‐in dynamic OR gates, IEEE Trans. Very Large Scale Integr. Syst. 18 (2010), no. 11, 1567-1577. https://doi.org/10.1109/TVLSI.2009.2025591
  14. A. Amirabadi et al., Clock delayed domino logic with efficient variable threshold voltage keeper, IEEE Trans. Very Large Scale Integr. Syst. 15 (2007), no. 2, 125-134. https://doi.org/10.1109/TVLSI.2007.891097
  15. A. Peiravi and M. Asyaei, Current‐comparison‐based domino: New low‐leakage high‐speed domino circuit for wide fan‐in gates, IEEE Trans. Very Large Scale Integr. Syst. 21 (2013), no. 5, 934-943. https://doi.org/10.1109/TVLSI.2012.2202408
  16. A. Peiravi and M. Asyaei, Robust low leakage controlled keeper by current‐comparison domino for wide fan‐in gates, Integration 45 (2012), no. 1, 22-32. https://doi.org/10.1016/j.vlsi.2011.07.002
  17. M. Asyaei and A. Peiravi, Low power wide gates for modern power efficient processors, Integration 47 (2014), no. 2, 272-283. https://doi.org/10.1016/j.vlsi.2013.08.005
  18. M. Asyaei, A new leakage‐tolerant domino circuit using voltage comparison for wide fan‐in gates in deep sub‐micron technology, Integration, VLSI J. 51 (2015), 61-71. https://doi.org/10.1016/j.vlsi.2015.06.003
  19. M. Asyaei and F. Moradi, A domino circuit technique for noise‐immune high fan‐in gates, J. Circuits, Syst. Comput. 27 (2018), no. 10 pp.1850151:1-23.
  20. F. Tang, A. Bermak, and Z. Gu, Low power dynamic logic circuit design using a pseudo dynamic buffer, Integration 45 (2012), no. 4, 395-404. https://doi.org/10.1016/j.vlsi.2011.08.003
  21. C. J. Akl and M. A. Bayoumi, Single‐phase SP‐domino: A limited‐switching dynamic circuit technique for low‐power wide fan‐in logic gates, IEEE Trans. Circuits Syst. II: Express Briefs 55 (2008), no. 2, 141-145. https://doi.org/10.1109/TCSII.2007.911836
  22. R. Singh et al., Static‐switching pulse domino: A switching‐aware design technique for wide fan‐in dynamic multiplexers, Integration 45 (2012), no. 3, 253-262. https://doi.org/10.1016/j.vlsi.2011.11.013
  23. M. Nasserian et al., A low‐power fast tag comparator by modifying charging scheme of wide fan‐in dynamic OR gates, Integration 52 (2016), no. 2, 129-141. https://doi.org/10.1016/j.vlsi.2015.09.004
  24. M. Asyaei and E. Ebrahimi, Low power dynamic circuit for power efficient bit lines, AEU‐Int. J. Electron. Commun. 83 (2018), 204-212. https://doi.org/10.1016/j.aeue.2017.08.048
  25. R. G. Jeyasingh, N. Bhat, and B. Amrutur, Adaptive keeper design for dynamic logic circuits using rate sensing technique, IEEE Trans. Very Large Scale Integr. Syst. 19 (2011), no. 2, 295-304. https://doi.org/10.1109/TVLSI.2009.2031650
  26. V. Kursun and E. G. Friedman, Domino logic with variable threshold voltage keeper, IEEE Trans. Very Large Scale Integr. Syst. 11 (2003), no. 6, 1080-1093. https://doi.org/10.1109/TVLSI.2003.817515
  27. J. Wang et al., Low power and high performance dynamic CMOS XOR/XNOR gate design, Microelectron. Eng. 88 (2011), no. 8, 2781-2784. https://doi.org/10.1016/j.mee.2011.02.068
  28. J. H. Wang et al., Performance estimation for dual threshold domino OR and the analysis for its availability under process variation, Chinese J. Electron 38 (2010), 2611-2615.
  29. S. O. Jung, K. W. Kim, and S. M. Kang, Noise constrained transistor sizing and power optimization for dual Vt domino logic, IEEE Trans. On Very Large Scale Integr. Syst. 10 (2002), no. 5, 532-541. https://doi.org/10.1109/TVLSI.2002.801625
  30. M. Alioto, G. Palumbo, and M. Pennisi, Understanding the effect of process variations on the delay of static and domino logic, IEEE Trans. Very Large Scale Integr. Syst. 18 (2010), no. 5, 697-710. https://doi.org/10.1109/TVLSI.2009.2015455

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