Journal of the Semiconductor & Display Technology (반도체디스플레이기술학회지)

The Korean Society Of Semiconductor & Display Technology (한국반도체디스플레이기술학회)
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Noise Modeling and Performance Evaluation in Nanoscale MOSFETs

나노 MOSFETs의 노이즈 모델링 및 성능 평가

  • Lee, Jonghwan (Department of System Semiconductor Engineering, Sangmyung University)
  • 이종환 (상명대학교 시스템반도체공학과)
  • Received : 2020.09.04
  • Accepted : 2020.09.16
  • Published : 2020.09.30
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Abstract

The comprehensive and physics-based compact noise models for advanced CMOS devices were presented. The models incorporate important physical effects in nanoscale MOSFETs, such as the low frequency correlation effect between the drain and the gate, the trap-related phenomena, and QM (quantum mechanical) effects in the inversion layer. The drain current noise model was improved by including the tunneling assisted-thermally activated process, the realistic trap distribution, the parasitic resistance, and mobility degradation. The expression of correlation coefficient was analytically described, enabling the overall noise performance to be evaluated. With the consideration of QM effects, the comprehensive low frequency noise performance was simulated over the entire bias range.

Keywords

References

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