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Electronics and Telecommunications Research Institute (한국전자통신연구원)
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GaAs on Si substrate with dislocation filter layers for wafer-scale integration

  • Kim, HoSung (Optical Communication Components Research Section, Photonic/Wireless Devices Research Division, Electronics and Telecommunications Research Institute) ;
  • Kim, Tae-Soo (Optical Communication Components Research Section, Photonic/Wireless Devices Research Division, Electronics and Telecommunications Research Institute) ;
  • An, Shinmo (Optical Communication Components Research Section, Photonic/Wireless Devices Research Division, Electronics and Telecommunications Research Institute) ;
  • Kim, Duk-Jun (Optical Communication Components Research Section, Photonic/Wireless Devices Research Division, Electronics and Telecommunications Research Institute) ;
  • Kim, Kap Joong (Quantum Optics Research Section, Quantum Technology Research Department, Electronics and Telecommunications Research Institute) ;
  • Ko, Young-Ho (Quantum Optics Research Section, Quantum Technology Research Department, Electronics and Telecommunications Research Institute) ;
  • Ahn, Joon Tae (Photonic Convergence Components Research Section, Photonic/Wireless Devices Research Division, Electronics and Telecommunications Research Institute) ;
  • Han, Won Seok (Optical Communication Components Research Section, Photonic/Wireless Devices Research Division, Electronics and Telecommunications Research Institute)
  • Received : 2021.01.06
  • Accepted : 2021.05.04
  • Published : 2021.10.01
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Abstract

GaAs on Si grown via metalorganic chemical vapor deposition is demonstrated using various Si substrate thicknesses and three types of dislocation filter layers (DFLs). The bowing was used to measure wafer-scale characteristics. The surface morphology and electron channeling contrast imaging (ECCI) were used to analyze the material quality of GaAs films. Only 3-㎛ bowing was observed using the 725-㎛-thick Si substrate. The bowing shows similar levels among the samples with DFLs, indicating that the Si substrate thickness mostly determines the bowing. According to the surface morphology and ECCI results, the compressive strained indium gallium arsenide/GaAs DFLs show an atomically flat surface with a root mean square value of 1.288 nm and minimum threading dislocation density (TDD) value of 2.4×107 cm-2. For lattice-matched DFLs, the indium gallium phosphide/GaAs DFLs are more effective in reducing the TDD than aluminum gallium arsenide/GaAs DFLs. Finally, we found that the strained DFLs can block propagate TDD effectively. The strained DFLs on the 725-㎛-thick Si substrate can be used for the large-scale integration of GaAs on Si with less bowing and low TDD.

Keywords

Acknowledgement

This work was supported by the Electronics and Telecommunications Research Institute (ETRI) grant funded by the Republic of Korea (21ZB1120, Development of creative technology for ICT) and the ICT R&D program of MSIP/IITP, Republic of Korea (018-0-00220, Development of low power on-board integrated 400-Gbps transmitting/receiving optical engine for hyper-scale data center; 2018-0-01632, Development of devices and components beyond single-carrier 400G for next generation optical transmission networks).

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