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1/64 Frequency-Divider design for high-frequency Phase-Locked Loop

고주파 위상동기회로를 위한 1/64 주파수 분주기 설계

  • Chae Jun Lee (Department of Electronic Semiconductor Engineering, Kangnam University)
  • 이채준 (강남대학교 전자반도체공학부)
  • Received : 2025.03.18
  • Accepted : 2025.05.20
  • Published : 2025.05.30
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Abstract

The RF transceiver system used in mobile communications(5G, 6G) consists of various circuits. Among them, the phase-locked loop (PLL) is an essential circuit for high-precision frequency synthesis. The PLL generates the desired high-precision frequency in RF circuits and is utilized for frequency conversion and channel selection. Additionally, it plays a crucial role in reducing phase variations and improving signal quality. By using the phase of the signal source as a reference, the PLL ensures the stability of the RF signal. This phase-locked loop consists of several sub-blocks, including a phase frequency detector (PFD), loop filter (LPF), voltage-controlled oscillator (VCO), and frequency divider. When all these blocks operate correctly, the input reference signal and the VCO output signal are compared, and the phase detector (PFD) detects the phase difference (Error Signal). The loop filter then processes this signal to generate a control voltage for the VCO, which adjusts its frequency accordingly. The frequency divider then divides the signal and feeds it back to the PFD. Once phase synchronization is achieved, the PLL outputs a stable frequency. In this paper, we introduce the design of a 1/64 frequency divider for high-frequency phase-locked loops. The goal is to achieve a stable phase-locked loop in high-frequency applications through the designed 1/64 frequency divider.

이동통신(5G, 6G)에서 사용되는 RF 송수신 시스템은 다양한 회로들로 구성되어 있다. 그 중 고정밀 주파수 합성을 위해 위상동기회로는 필수적으로 필요한 회로이다. 위상동기 회로는 RF회로에서 원하는 고정밀 주파수를 생성하며, 주파수 변환 및 채널 선택에 활용된다. 또한 위상 변동을 줄여 신호의 품질을 향상시키는 중요한 회로 블락이다. 신호원의 위상을 기준으로 삼아 RF 신호를 안정적으로 유지한다. 위 위상 동기회로는 여러 가지 세부 블락[위상검출기(PFD), 루프필터(LF), 전압 제어 발진기(VCO), 주파수 분주기(FD) 등]으로 구성되어 있다. 각 블록이 정상적으로 동작했을 때, 입력 신호(Reference Signal)와 VCO 출력 신호의 위상을 비교 후 위상 검출기(PFD)가 위상 차이(Phase Error)를 검출한다. 이후 루프 필터(LF)가 신호를 필터링하여 VCO 제어 전압을 생성하고 VCO가 제어 전압에 따라 주파수를 조정하며, 주파수 분주기(Divider)가 신호를 나누어 다시 위상 검출기(PFD)로 피드백되어 위상 동기화가 완료되면 PLL은 안정적인 주파수를 출력하는 방법으로 동작한다. 본 논문에서는 PLL을 구성하는 블락 중 고주파 위상동기회로를 위한 1/64 주파수 분주기 설계에 대한 내용을 다룬다. 논문에서 소개한 1/64 분주기를 통해 고주파에서 안정적인 위상동기회로 구현을 목표로 한다.

Keywords

Acknowledgement

This Research was Supported by Kangnam University Research Grants(2025)

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