• 반도체디스플레이기술학회지
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• 제5권2호
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• pp.47-49
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• 2006

Various methods of making thin film is being used in semiconductor manufacturing process. The most common method in this field includes CVD(Chemical Vapor Deposition) and PVD(Physical Vapor Deposition). Thin film is deposited on both the backside and the frontside of wafers. The thin film deposited on the backside has poor thickness profile, and can contaminate wafers in the following processes. If wafers with the thin film remaining on the backside are immersed in batch type process tank, the thin film fall apart from the backside and contaminate the nearest wafer. Thus, it is necessary to etch the backside of the wafer selectively without etching the frontside, and chemical injection nozzle positioned under the wafer can perform the backside etching. In this study, the backside chemical injection nozzle with optimized chemical injection profile is built for single wafer tool. The evaluation of this nozzle, performed on $Si_3N_4$ layer deposited on the backside of the wafer, shows the etching rate uniformity of less than 5% at the etching rate of more than $1000{\AA}$.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제43회 하계 정기 학술대회 초록집
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• pp.319-320
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• 2012

Large aperture optical modulator called optical shutter is a key component to realize time-of-flight (TOF) based three dimensional (3D) imaging systems [1-2]. The transmission type electro-absorption modulator (EAM) is a prime candidate for 3D imaging systems due to its advantages such as small size, high modulation performance [3], and ease of forming two dimensional (2D) array over large area [4]. In order to use the EAM for 3D imaging systems, it is crucial to remove GaAs substrate over large area so as to obtain high uniformity modulation performance at 850 nm. In this study, we propose and experimentally demonstrate techniques for backside etching of GaAs substrate over a large area having high uniformity. Various methods such as lapping and polishing, dry etching for anisotropic etching, and wet etching ([20%] C6H8O7 : H2O2 = 5:1) for high selectivity backside etching [5] are employed. A high transmittance of 80% over the large aperture area ($5{\times}5mm^2$) can be obtained with good uniformity through optimized backside etching method. These results reveal that the proposed methods for backside etching can etch the substrate over a large area with high uniformity, and the EAM fabricated by using backside etching method is an excellent candidate as optical shutter for 3D imaging systems.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
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• pp.237-240
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• 2001

In this paper, we have presented processing technique about wet etching for silicon membrane construction formation. In order to make selective etching of backside silicon wafer, we used Si$_3$N$_4$ layer by PECVD(Plasma Enhanced Chemical Vapor Deposition). We have measured the surface thickness in backside silicon wafer after anisortropic wet etching with KOH:distilled water solutions. Through this experiment, we acquired the etching rate for 1.29${\mu}{\textrm}{m}$/min. The average rough of Si-membrane frontside and backside was 0.26${\mu}{\textrm}{m}$, 0.90${\mu}{\textrm}{m}$, respectively.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2013년도 제45회 하계 정기학술대회 초록집
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• pp.220-220
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• 2013

Surface-normal transmission electro-absorption modulator (EAM) are attractive for high-definition (HD) three-dimensional (3D) imaging application due to its features such as small system volume and simple epitaxial structure [1,2]. However, EAM in order to be used for HD 3D imaging system requires uniform modulation performance over large area. To achieve highly uniform modulation performance of EAM at the operating wavelength of 850 nm, it is extremely important to remove the GaAs substrate over large area since GaAs material has high absorption coefficient below 870 nm which corresponds to band-edge energy of GaAs (1.424 eV). In this study, we propose and experimentally demonstrate a transmission EAM in which highly selective backside etching methods which include lapping, dry etching and wet etching is carried out to remove the GaAs substrate for achieving highly uniform modulation performance. First, lapping process on GaAs substrate was carried out for different lapping speeds (5 rpm, 7 rpm, 10 rpm) and the thickness was measured over different areas of surface. For a lapping speed of 5 rpm, a highly uniform surface over a large area ($2{\times}1\;mm^2$) was obtained. Second, optimization of inductive coupled plasma-reactive ion etching (ICP-RIE) was carried out to achieve anisotropy and high etch rate. The dry etching carried out using a gas mixture of SiCl4 and Ar, each having a flow rate of 10 sccm and 40 sccm, respectively with an RF power of 50 W, ICP power of 400 W and chamber pressure of 2 mTorr was the optimum etching condition. Last, the rest of GaAs substrate was successfully removed by highly selective backside wet etching with pH adjusted solution of citric acid and hydrogen peroxide. Citric acid/hydrogen peroxide etching solution having a volume ratio of 5:1 was the best etching condition which provides not only high selectivity of 235:1 between GaAs and AlAs but also good etching profile [3]. The fabricated transmission EAM array have an amplitude modulation of more than 50% at the bias voltage of -9 V and maintains high uniformity of >90% over large area ($2{\times}1\;mm^2$). These results show that the fabricated transmission EAM with substrate removed is an excellent candidate to be used as an optical shutter for HD 3D imaging application.

• 반도체디스플레이기술학회지
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• 제19권2호
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• pp.77-81
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• 2020

Silicon wafer etching in micro electro mechanical systems (MEMS) fabrication is challenging to form 3-D structures. Well known Si-wet etch of silicon employs potassium hydroxide (KOH), tetramethylammonium hydroxide (TMAH) and sodium hydroxide (NaOH). However, the existing silicon wet etching process has a fatal disadvantage that etching of the back side of the wafer is hard to avoid. In this study, a wet etching bath for 150 mm wafers was designed to prevent back-side etching of silicon wafer, and we demonstrated the optimized process recipe to have anisotropic wet etching of silicon wafer without any damage on the backside. We also presented the design of wet bath for 300 mm wafer processing as a promising process development.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 하계종합학술대회 논문집(2)
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• pp.68-71
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• 2000

In this paper, we have measured the oxygen contents by FTIR in silicon wafer various process technology(slicing, lapping, polishing). The measured data are also compared with the data of etching process(KOH, Bright etching). Also we have measured the surface morpology in backside silicon wafer after etching treatment and etch pit density due to OISF after 4 step high temperature annealing process with optical microscope.

• 한국정밀공학회지
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• 제31권1호
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• pp.75-81
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• 2014

Laser beam machining has been known as efficient for glass micromachining. It is usually used the ultra-short pulsed laser which is time-consuming and uneconomic process. In order to use economic and powerful long pulsed laser, indirect processing called laser-induced backside wet etching (LIBWE) is good alternative method. In this paper, micromachining of glass using Nd:YAG laser with nanosecond pulsed beam has been attempted. In order to improve shape accuracy, combined processing with magnetic stirrer has been widely used. Magnetic stirrer acts to circulate the solution and remove the bubble but it is not suitable for deep hole machining. To get better effect, ultrasonic vibration was applied for improving shape accuracy.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2012년도 추계학술대회 논문집
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• pp.353-354
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• 2012

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2013년도 춘계학술대회 논문집
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• pp.151-152
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• 2013

• 전자공학회논문지A
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• 제30A권1호
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• pp.16-22
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• 1993

A via-hole process for reproducible and reliable GaAs MMIC fabrication is described. The via-hole etching process consists of two step dry etching. During the first etching step a BC $I_{3}$/C $I_{2}$/Ar gas mixure is used to achieve high etch rate and small lateral etching. In the second etching step. CC $L_{2}$ $F_{2}$ gas is used to achieve selective etching of the GaAs substrate with respect to the front side metal layer. Via holes are formed from the backside of a 100$\mu$m thick GaAs substrate that has been evaporated initially with 500.angs. thick chromium and subsequently a 2000.angs. thick gold layer. The fabricated via holes are electroplated with gold (~20$\mu$m thick) to form via connections. The results show that established via-hole process is satisfactory for GaAs MMIC fabrication.