• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.3
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• pp.411-424
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• 2017

An all-digital delay-locked loop (DLL) for a mobile memory interface, which runs at 0.11-2.5 GHz with a phase-shift capability of $180^{\circ}$, has two internal DLLs: a global DLL which uses a time-to-digital converter to assist fast locking, and shuts down after locking to save power; and a local DLL which uses a phase detector with an adaptive phase sampling window (WPD) to reduce jitter accumulation. The WPD in the local DLL adjusts the width of its sampling window adaptively to control the loop bandwidth, thus reducing jitter induced by UP/DN dithering, input clock jitter, and supply/ground noise. Implemented in a 65 nm CMOS process, the DLL operates over 0.11-2.5 GHz. It locks within 6 clock cycles at 0.11 GHz, and within 17 clock cycles at 2.5 GHz. At 2.5 GHz, the integrated jitter is $954fs_{rms}$, and the long-term jitter is $2.33ps_{rms}/23.10ps_{pp}$. The ratio of the RMS jitter at the output to that at the input is about 1.17 at 2.5 GHz, when the sampling window of the WPD is being adjusted adaptively. The DLL consumes 1.77 mW/GHz and occupies $0.075mm^2$.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.05a
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• pp.95-98
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• 2012

This paper describes a multiphase delay-locked loop (DLL) that generates a 32-phase output clock over the operating frequency range of 40 MHz to 280 MHz. The matrix-based delay line is used for high resolution of 1-bit delay. A calibration scheme, which improves the linearity of a delay line, is achieved by calibrating the nonlinearity of the input stage of the matrix. The multi-phase DLL is fabricated by using 0.11-${\mu}m$ CMOS process with a 1.2 V supply. At the operating frequency of 125MHz, the measurement results shows that the DNL is less than +0.51/-0.12 LSB, and the measured peak-to-peak jitter of the multi-phase DLL is 30 ps with input peak-to-peak jitter of 12.9 ps. The area and power consumption of the implemented DLL are $480{\times}550{\mu}m^2$ and 9.6 mW at the supply voltage of 1.2 V, respectively.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.12
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• pp.33-39
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• 2013

There have been studies in improving jitter characteristic of delay locked loop (DLL) even it has a shorter jitter that of phase locked loop (PLL). These studies result in numerous architectures of DLL which improve jitter performance. The paper shows that the jitter characteristic can be improved with various loop filters in DLL. It has been designed with 1.8V $0.18{\mu}m$ CMOS process.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.4
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• pp.264-269
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• 2006

A $0.12GHz{\sim}1.4GHz$ DLL-based clock generator with the capability of multiplied four phase clock generation was designed using a 0.18um CMOS process. An adaptive bandwidth DLL with a regulated supply delay line was used for a multiphase clock generation and a low jitter. An extra phase detector (PD) in a reference DLL solves the problem of the initial VCDL delay and achieves a fast lock time. Twice multiplied four phase clocks were generated at the outputs of four edge combiners, where the timing alignment was achieved using a coarse lock signal and the 10 multiphase clocks with T/8 time difference. Those four clocks were combined one more time using a static XOR circuit. Therefore the four times multiplication was achieved. With a 1.8V supply, the rms jitter of 2.1ps and the peak-to-peak jitter of 14.4ps were measured at 1.25GHz output. The operating range is $0.12GHz{\sim}1.4GHz$. It consumes 57mW and occupies 450*325um2 of die area.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.10a
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• pp.394-397
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• 2003

Since the speed of operation in the system has been increasing rapidly, chips should have been synchronized. Then, synchronized circuits such as PLL (Phase Locked Loop), DLL (Delay Locked Loop) are used. VCO (Voltage Controled Oscillator) generated a frequency in the PLL has disadvantage such as jitter accumulation. On the other hands, VCDL (Voltage Controled Delay Line) used at DLL has an advantage which has no jitter accumulation. In this paper, a new and improved VCDL structure is suggested.

• Journal of IKEEE
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• v.21 no.4
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• pp.416-419
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• 2017

In this paper, we propose a new digital delay-locked loop (DLL) for high-speed DDR3/DDR4 SDRAMs. The proposed digital DLL adopts a fine delay line using phase interpolation to eliminate the jitter increase problem due to the boundary switching problem. In addition, the proposed digital DLL utilizes a new gradual search algorithm to eliminate the harmonic lock problem. The proposed digital DLL is designed with a 1.1 V, 38-nm CMOS DRAM process and has a frequency operating range of 0.25-2.0 GHz. It has a peak-to-peak jitter of 1.1 ps at 2.0 GHz and has a power consumption of about 13 mW.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.4
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• pp.520-527
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• 2016

A new dual-loop digital delay-locked loop (DLL) using a hybrid (binary + sequential) search algorithm is presented to achieve both wide-range operation and high delay resolution. A new phase-interpolation range selector (PIRS) and a variable successive approximation register (VSAR) algorithm are adopted to resolve the boundary switching and harmonic locking problems of conventional digital DLLs. The proposed digital DLL, implemented in a $0.18-{\mu}m$ CMOS process, occupies an active area of $0.19mm^2$ and operates over a wide frequency range of 0.15-1.5 GHz. The DLL dissipates a power of 11.3 mW from a 1.8 V supply at 1 GHz. The measured peak-to-peak output clock jitter is 24 ps (effective pk-pk jitter = 16.5 ps) with an input clock jitter of 7.5 ps at 1.5 GHz. The delay resolution is only 2.2 ps.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.963-964
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• 2006

By combining a digital DLL and an analog DLL in 2-stage, an improved DLL is implemented in this paper. The proposed DLL is composed of a RDLL (Register Controlled DLL) and a conventional analog DLL. The phase comparator used in the DLL is built with sense-amp based D flip-flops for high speed operation. The proposed DLL circuits have been designed, simulated in 0.18um, 1.8V TSMC CMOS library. The implemented DLL have demonstrated the fast lock-on time of 1us and low jitter of 72ps.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.281-284
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• 2001

This paper describes an analog multi-phase delay-locked loop (DLL) to solve the harmonic lock problem using current-starved inverter and shunt-capacitor delay cell. The DLL can be used not only as an internal clock buffer of microprocessors and memory It's but also as a multi-phase clock generator for gigabit serial interfaces. The proposed circuit was simulated in a 0.25${\mu}{\textrm}{m}$ CMOS technology to solve harmonic lock problem and to realize fast lock-on time and low-jitter we verified time interval less than 40 ps as the simulation results.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.259-262
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• 2012

This paper describes a delay-locked loop (DLL) that generates a 64-phase clock with the operating frequency of 125MHz. The proposed DLL use a $4{\times}8$ matrix-based delay line to improve the linearity of a delay line. The output clock with 64-phase is generated by using a CMOS multiplex and a inverted-based interpolator from 32-phase clock which is the output clock of the $4{\times}8$ matrix-based delay line. The circuit for an initial phase lock, which is independent on the duty cycle ratio of the input clock, is used to prevent from the harmonic lock of a DLL. The proposed DLL is designed using a $0.18-{\mu}m$ CMOS process with a 1.8 V supply. The simulated operating frequency range is 40 MHz to 200 MHz. At the operating frequency of a 125 MHz, the worst phase error and jitter of a 64-phase clock are +11/-12 ps and 6.58 ps, respectively.