• Proceedings of the KIPE Conference
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• 2000.07a
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• pp.163-167
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• 2000

This paper presents the digital control of single-phase power factor correction(PFC) converter which has the variable gain according to the condition of inner control loop error. Generally the gain of inner current control loop in single-stage PFC converter has a constant magnitude. This has a bad influence on the power factor because current loop doesn't operate smoothly in the condition that input voltage is low In particular a digital controller has more time delay than an analog controller and degrades This drops the phase margin of the total digital PFC system,. It causes the problem that the gain of current control loop isn't increased enough. In addition the oscillation happens in the peak value of the input voltage open loop PFC system gain changes according to ac input voltage. These aspects make the design of the digital PFC controller difficult The digital PFC controller presented in this paper has a variable gain of current control loop according to input voltage. The 1kW converter was used to verify the efficiency of the digital PFC controller.

• Journal of electromagnetic engineering and science
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• v.17 no.3
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• pp.138-146
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• 2017

A phase-locked dielectric resonator oscillator (PLDRO) is an essential component of millimeter-wave communication, in which phase noise is critical for satisfactory performance. The general structure of a PLDRO typically includes a dual loop of digital phase-locked loop (PLL) and analog PLL. A dual-loop PLDRO structure is generally used. The digital PLL generates an internal voltage controlled crystal oscillator (VCXO) frequency locked to an external reference frequency, and the analog PLL loop generates a DRO frequency locked to an internal VCXO frequency. A dual loop is used to ease the phase-locked frequency by using an internal VCXO. However, some of the output frequencies in each PLL structure worsen the phase noise because of the N divider ratio increase in the digital phase-locked loop integrated circuit. This study examines the design aspects of an interconnected PLL structure. In the proposed structure, the voltage tuning; which uses a varactor diode for the phase tracking of VCXO to match with the external reference) port of the VCXO in the digital PLL is controlled by one output port of the frequency divider in the analog PLL. We compare the proposed scheme with a typical PLDRO in terms of phase noise to show that the proposed structure has no performance degradation.

• ETRI Journal
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• v.29 no.4
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• pp.463-469
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• 2007

A phase-locked loop (PLL) is described which is operable from 0.4 GHz to 1.2 GHz. The PLL has basically the same architecture as the conventional analog PLL except the locking information is stored as digital code. An analog-to-digital converter is embedded in the PLL, converting the analog loop filter output to digital code. Because the locking information is stored as digital code, the PLL can be turned off during power-down mode while avoiding long wake-up time. The PLL implemented in a 0.18 ${\mu}m$ CMOS process occupies 0.35 $mm^2$ active area. From a 1.8 V supply, it consumes 59 mW and 984 ${\mu}W$ during the normal and power-down modes, respectively. The measured rms jitter of the output clock is 16.8 ps at 1.2 GHz.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1987.04a
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• pp.82-85
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• 1987

This paper describes the technology for the improvement of subxdriber loop utilization. Nearly all customer loops are now carried at voice frequency on individual wire pairs. Reenct digital technology improvements together with the increasing cost of wire, have resulted in some penetration of carrier systems into the loop plant. Moreover the increasing use of local digital switching systems should permit digital carrier systems to become an important factor in the loop plant in the future.

• Journal of the Korea Society of Computer and Information
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• v.4 no.2
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• pp.105-112
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• 1999

Spread Spectrum Communication is a core technique in CDMA system, but the problem for SS Communication schemes is synchronous method. There are DLL(Delay Lock Loop), Tau-dither Loop, SO(Synchronous Osillator) etc., in the sychronous method. But since there are analog operations, the setting is difficult and circuit size is large. In this paper we proposed Digital Delay Lock Loop (DDLL) and estimated it's performance through the experiment.

• Journal of Power Electronics
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• v.11 no.2
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• pp.113-119
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• 2011

This paper presents a DSP based direct digital control design and implementation for a high power boost converter. A single loop and dual loop voltage control are digitally implemented and compared. The real time workshop (RTW) is used for automatic real-time code generation. Experimental results of a 20 kW boost converter based on the TMS320F2808 DSP during reference voltage changes, input voltage changes, and load disturbances are presented. The results show that the dual loop control achieves better steady state and transient performance than the single loop control. In addition, the experimental results validate the effectiveness of using the RTW for automatic code generation to speed up the system implementation.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.48 no.9
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• pp.1131-1139
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• 1999

In this paper, we present a wide-bandwidth digital rebalance loop for a dynamically tuned gyroscope(DTG) based on {{{{ { H}_{2 } }}}} methodology. The operational principle and the importance of a rebalance loop are explaind, first. The augmented plant model is constructed, which includes a gyroscope model and an integrator. An {{{{ { H}_{ 2} }}}} based controller is designed for the augmented plant model. To verify the performance of the controller, a digital rebalance loop for a DTG is designed, fabricated and experimented. Through frequency response analyses and experiments using a real DTG, it is confirmed that the controller is more robustly stable and has a wider bandwidth compared with those of a conventional PID controller, contributing to the performance improvement of a DTG.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.8
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• pp.2043-2054
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• 1996

In this paper, Digital Delay Locked Loop(DDLL) is designed, implemented and analysed by experiment whose results show that it is possible to track the received signal by this scheme. Designed digital DLL has an advantage that it is not needed to maintain gain balance between early and late channels, which has been problem with an analog DLL. Also DDLL has more improved noise performance compared to analog DLL due to noise level limitation and noise cancellation characteristics. For various loop parameters, their effects on loop performance are analysed and simulated. Proposed DDLL is the first attempt as a digital approach in code tracking loop and it is expected to be a good reference for spread spectrum communication research.

• Journal of Power Electronics
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• v.10 no.5
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• pp.518-527
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• 2010

This paper presents a new technique for directly designing a linear digital controller for a single-phase pulse width modulation (PWM) converter systems, based on closed-loop identification. The design procedure consists of three steps. First, obtain a digital current controller for the inner loop system by using the error space approach, so that the power factor of the supply is close to one. The outer loop is composed of a voltage controller, a current control loop including a current controller, a PWM converter, and a capacitor. Then, all the components, except the voltage controller, are identified by a discrete-time equivalent linear model, using the closed-loop output error (CLOE) method. Based on this equivalent model, a proper digital voltage controller is then directly designed. It is shown through PSim simulations and experimental results that the proposed method is useful for the practical design of PWM converter controllers.

• Korean Journal of Optics and Photonics
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• v.13 no.5
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• pp.377-383
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• 2002

An all-digital closed-loop (ADCL) signal processor for an open-loop FOG was developed to replace the analog circuitry of a Digital Phase Tracking (DPT) signal processor with new digital circuitry. When the ADCL signal processor without a stabilizer for fiber phase modulator (FPM) was attached to the FOG, temperature drift of FOG was about 0.26$\mu$rad/$^{\circ}C$, which makes the FOG unusable in medium or higher-grade applications. This drift was due to variations of phase modulation amplitude and phase delay of the FPM. The stabilizer controls its phase modulation amplitude and phase delay by regulating the ratio of harmonics of the FOG output. Thus, the stabilizer reduces the drift of the FOG to negligible.