• The Transactions of the Korean Institute of Power Electronics
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• v.10 no.3
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• pp.290-295
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• 2005

The incremental encoder has been mostly used to measure the speed and position of the motor. As the output signals of encoder are high frequency digital signals, they have much influence on radiation noises due to switching of the power semiconductor circuits. It is so difficult to suppress the noises with the conventional LPF. In this paper, the hardware digital filter for suppressing noises in the output signals of the encoder signals is developed. As both the clock frequency and counter in the digital filter for encoder are easily adjusted according to the kinds of noises, any noises in the encoder can be entirely eliminated. The performance of the digital filter has been verified by simulation and experimental results.

• 제어로봇시스템학회:학술대회논문집
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• 1997.10a
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• pp.241-244
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• 1997

A dead reckoning navigation system is developed for autonomous mobile robot localization. The navigation system was implemented by novel sensor fusion using a Kalman filter. A differential encoder and the gyroscope error models are developed for the filter. An indirect Kalman filter scheme is adopted to reduce the computational burden and to enhance the navigation system reliability. The filter mutually compensates the encoder errors and the gyroscope errors. The experimental results show that the proposed mobile . robot navigation algorithm provides the reliable position and heading angle of the mobile robot without any help of the external positioning systems.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.3
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• pp.511-516
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• 2006

In this raper, we propose the Sequentiel Couleur Avec Memoire or Sequential Color with Memory (SECAM) video encoder system using modified anti-cloche filters and the SECAM video decoder system using a band pass filter (BPF) and an error-free square root. The SECAM encoder requires an anti-cloche filter recommended by International Telecommunication Union-Recommendation (ITU-R) Broadcasting service Television (BT) 470. However, the design of the anti-cloche filter is difficult because the frequency response of the anti-cloche filter is very sharp around rejection-frequency area. So, we convert the filter into a hish pass filter (HPF) by shifting the rejection frequency of 4.286MHz to 0Hz frequency. The design of HPF becomes very easy, compared to that of the anti-cloche filter. The proposed decoder also uses an error-free square root, two differentiators and trigonometric functions to extract color-component information of Db and Dr accurately from frequency modulation (FM) signals in SECAM systems. Also, the BPF in decoder it used for removing color noise in chrominance and dividing CVBS into chrominance and luminance. The proposed systems are experimentally demonstrated with Altera FPGA APEX20KE EP20K1000EBC652-3 device and TV sets.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.401-404
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• 2015

This paper proposes a high-performance in-loop filter in HEVC(High Efficiency Video Coding) encoder for Ultra HD video processing in real time. HEVC uses in-loop filter consisting of deblocking filter and SAO(Sample Adaptive Offset) to solve the problems of quantization error which causes image degradation. In the proposed in-loop filter encoder hardware architecture, the deblocking filter and SAO has a 2-level hybrid pipeline structure based on the $32{\times}32CTU$ to reduce the execution time. The deblocking filter is performed by 6-stage pipeline structure, and it supports minimization of memory access and simplification of reference memory structure using proposed efficient filtering order. Also The SAO is implemented by 2-statge pipeline for pixel classification and applying SAO parameters and it uses two three-layered parallel buffers to simplify pixel processing and reduce operation cycle. The proposed in-loop filter encoder architecture is designed by Verilog HDL, and implemented by 205K logic gates in TSMC 0.13um process. At 110MHz, the proposed in-loop filter encoder can support 4K Ultra HD video encoding at 30fps in realtime.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.10
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• pp.199-203
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• 2013

In this paper, a fast algorithm of discrete cosine transform-based interpolation filter (DCT-IF) for HEVC (high efficiency video coding) encoder is proposed. DCT-IF filter accounts for around 30% of encoder complexity, according to the computational complexity analysis with the HEVC reference software. In this work, the proposed DCT-IF is optimized by applying frame-level interpolation, SIMD optimization, and task-level parallelization via OpenMP on a developed C-based HEVC encoder. Performance analysis is conducted by measuring speed-up factor of the proposed optimization technique on the developed encoder. The results show that speed-up factors by frame-level interpolation, SIMD, and OpenMP are approximately 38-46, 3.6-4.4, and 3.0-3.7, respectively. In the end, we achieved the speed-up factor of 498.4 with the proposed fast algorithm.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.11C
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• pp.1083-1090
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• 2005

This paper presents the design of a video encoder for the device of need TV-OUT function. The designed video encoder satisfies the standard conditions of International Telecommunication Union-Radiocommunication (ITU-R) BT.470. ITU-R BT.470 can be classified as NTSC, PAL or SECAM. NTSC and PAL use Amplitude Modulation (AM) to transmit color difference signals and SECAM uses Frequency Modulation (FM). SECAM must have an antic-cloche filter but the filter recommended by ITU-R BT.470 is not easy to design due to sharpness of the frequency response. So formerly the filter was designed as analog. This paper proposes that the filter is designed as digital and the special quality of the filter is transformed easy to design. And the modulation method is modified to be identical with the result required at standard. The encoder can control power consumption by output mode to apply mobile phone, mobile devices, etc. The proposed encoder is experimentally demonstrated with ALTERA FPGA APEX20KE EP20K1000EBC652-3 device and SAMSUNG LCD-TV.

• Proceedings of the KIEE Conference
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• 2005.05a
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• pp.170-172
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• 2005

The DSD(Direct Stream Digital) encoder, which is a standard for SACD(Super Audio Compact Disc) proposed by Sony and philips, use 1 bit representation with a sampling frequency of 2.8224 MHz (64 $\times$ 44.1 kHz). For multi-rate PCM (Pulse Code Modulation) input like as 48/96/192 kHz, a external sample-rate converter is necessary to the DSD encoder. This paper has been proposed a digital filter structure composed of sample-rate converter and interpolation filter for the DSD encoder with multi-rate (48/96/192 kHz) PCM input. without a external sample-rate converter.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.2
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• pp.335-342
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• 2016

This paper proposes efficient hardware structure of in-loop filter for a high-performance HEVC (High Efficiency Video Coding) encoder. HEVC uses in-loop filter consisting of deblocking filter and SAO (Sample Adaptive Offset) to improve the picture quality in a reconstructed image due to a quantization error. However, in-loop filter causes an increase in complexity due to the additional encoder and decoder operations. A proposed in-loop filter is implemented as a three-stage pipeline to perform the deblocking filtering and SAO operation with a reduced number of cycles. The proposed deblocking filter is also implemented as a six-stage pipeline to improve efficiency and performs a new filtering order for efficient memory architecture. The proposed SAO processes six pixels parallelly at a time to reduce execution cycles. The proposed in-loop filter encoder architecture is designed by Verilog HDL, and implemented by 131K logic gates in TSMC $0.13{\mu}m$ process. At 164MHz, the proposed in-loop filter encoder can support 4K Ultra HD video encoding at 60fps in real time.

• Proceedings of the KIEE Conference
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• 2005.10b
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• pp.584-586
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• 2005

In this paper, low cost inertial sensor and compass were used instead of encoder for localization of mobile robot. Movements by encoder, movements by inertial sensor and movements by complementary filter with inertial sensor and compass were analyzed. Movement by complementary filter was worse than by only inertial sensor because of imperfection of compass. For the complementary filter to show best movements, compass need to be compensated for position error.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.100-103
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• 2008

In this paper, we propose H.264 Encoder integrating Intra Prediction, Deblocking filter, Context-Based Adaptive Variable Length Coding, and Motion Estimation encoder module. This designed module can be operated in 440 cycle for one-macroblock. To verify the Encoder architecture, we developed the reference C from JM 9.4 and verified the our developed hardware using test vector generated by reference C. The designed circuit can be operated in 166MHz clock system, and has 1800k gate counts using Charterd 0.18um process including SRAM memory. Manufactured chip has the size of $6{\times}6mm$ and 208 pins package.