• The Journal of the Acoustical Society of Korea
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• v.18 no.1
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• pp.3-9
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• 1999

This paper concerns performance of a parallel digital signal processing system. The performance of the system is analyzed in terms of CPU cycles required for 1024-point FFT computation. The number of cycles is estimated in three different approaches; FFT algorithm-based, assembly level source code-based, and probability-based. The results of analysis indicate that on a bus-based system the best performance for FFT is achieved with a single board. Because in some applications like FFT, where frequent data exchanges among processors occur, the number of communication cycles increases as the number of boards. It is observed that inter-board communication degrades overall system performance for the FFT computation. Also shown is that linear increase in performance can be obtained if multiple buses are employed.

• The Journal of the Acoustical Society of Korea
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• v.27 no.3
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• pp.149-153
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• 2008

General underwater target detection methods adopt short-time FFT for estimate target doppler. This paper proposes the efficient target detection method, instead of conventional FFT, using approximate FFT for distributed sensor network target detection, which requires lighter computations. In the proposed method, we decrease computational rate of FFT by the quantization of received signal. For validation of the proposed method, experiment result which is applied to FFT based active sonar detector and real oceanic data is presented.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.48 no.4
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• pp.53-60
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• 2011

In order to augment the robustness of OFDM system to Rayleigh multipath fading, there exist two smart antenna algorithms, namely, Pre-FFT smart antenna and Post-FFT smart antenna. After the mathematical modeling of both smart antenna algorithms, computer simulations have been carried to compare and analyze the performance of generalized eigen problem based Pre-FFT algorithm and the performance of Wiener solution based Post-FFT algorithm. It has been shown that the Post-FFT smart antenna far outperforms the Pre-FFT smart antenna due to the computational complexities. Especially it is so when the multipath signal arrives at beyond the guard interval and a rich co-channel interferer is introduced. Performance of a subcarrier clustering method proposed to lessen the computing load has been compared to that of a typical Wiener solution based Post-FFT smart antenna. Performance comparison between MRC(Maximum Ratio Combining) diversity based Post-FFT algorithm and typical Post-FFT algorithm has also been carried.

• Journal of Digital Convergence
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• v.11 no.2
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• pp.287-297
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• 2013

In this paper, we propose an efficient variable-length radix-8/4/2 FFT architecture for OFDM systems. The FFT processor is based on radix-8 FFT algorithm and also supports radix-4 or radix-2 FFT computation. We are using efficient "In-place" memory access method to maintain conflict-free data access and minimize memory size. Also we replace a very large lookup table with a twiddle factor generator which consumes less area then a ROM-based lookup table. The proposed FFT processor performs variable-length FFT including 64, 256, 512, 1024, 2048, 4096 and 8192 points which cover all the required FFT lengths used in 802.11a, 802.16a, DAB, DVB-T, VDSL and ADSL.

• Journal of Advanced Navigation Technology
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• v.22 no.5
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• pp.429-435
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• 2018

In radar systems, FFT (fast Fourier transform) operation is necessary to obtain the range and velocity of target, and the design of an FFT processor which operates at high speed is required for real-time implementation. The perfect shuffle network is suitable for high-speed FFT processor. In particular, twice perfect shuffle network based on radix-4 is preferred for very high-speed FFT processor. Moreover, radar systems that requires various velocity resolution should support scalable FFT points. In this paper, we propose a 8~1024-point scalable FFT processor based on twice perfect shuffle network algorithm and present hardware design and implementation results. The proposed FFT processor was designed using hardware description language (HDL) and synthesized to gate-level circuits using $0.65{\mu}m$ CMOS process. It is confirmed that the proposed processor includes logic gates of 3,293K.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.7A
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• pp.1005-1015
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• 1999

This paper is concerned with an improvement on IFFT (inverse fast Fourier transform) and FFT based baseband digital implementation algorithm for BPSK (binary phase shift keying)-modulated MC-CDMA (multicarrier-code division multiple access) systems, that is functionally equivalent to the conventional implementation algorithm, while reducing computational complexity and bandwidth requirement. We also derive an equalizer structure for the proposed implementation algorithm. The proposed algorithm is based on a variant of FFT algorithm that utilizes a N/2-point FFT/IFFT for simultaneous transformation and reconstruction of two N/2-point real signals. The computer simulations under additive white Gaussian noise channels and frequency selective fading channels using equal gain combiner and maximal ratio combiner diversities, demonstrate the performance of the proposed algorithm.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.1
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• pp.205-212
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• 2010

This paper describes a core generator (FCore_Gen) which generates Verilog-HDL models of 640 different FFT/IFFT cores with selected parameter value for OFDM-based communication systems. The generated FFT/IFFT cores are based on in-place single memory architecture and use a hybrid structure of radix-4 and radix-2 DIF algorithm to accommodate various FFT lengths. To achieve both memory reduction and the improved SQNR, a conditional scaling technique is adopted, which conditionally scales the intermediate results of each computational stage. The cores synthesized with a $0.35-{\mu}m$ CMOS standard cell library can operate with 75-MHz@3.3-V, and a 8,192-point FFT can be computed m $762.7-{\mu}s$, thus the cores satisfy the specifications of wireless LAN, DMB, and DVB systems.

• ETRI Journal
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• v.30 no.3
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• pp.451-460
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• 2008

Recently, the power consumption of integrated circuits has been attracting increasing attention. Many techniques have been studied to improve the power efficiency of digital signal processing units such as fast Fourier transform (FFT) processors, which are popularly employed in both traditional research fields, such as satellite communications, and thriving consumer electronics, such as wireless communications. This paper presents solutions based on parallel architectures for high throughput and power efficient FFT cores. Different combinations of hybrid low-power techniques are exploited to reduce power consumption, such as multiplierless units which replace the complex multipliers in FFTs, low-power commutators based on an advanced interconnection, and parallel-pipelined architectures. A number of FFT cores are implemented and evaluated for their power/area performance. The results show that up to 38% and 55% power savings can be achieved by the proposed pipelined FFTs and parallel-pipelined FFTs respectively, compared to the conventional pipelined FFT processor architectures.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.9
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• pp.2121-2126
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• 2013

This paper compares radix-2 based structures for 32768-point FFT. Radix-$2^k$ structures have been widely used because the butterfly is simple and the number of multipliers can be reduced in those structures. This paper applied various radix-$2^k$ structures to 32768-point FFT that is representing ultra-long FFT. The ultra-long FFT has been studied much recently. This paper shows that the radix-$2^4$ structure is the most adequate because it shows the smallest complexity in the synthesis and the best SQNR performance. should be placed here.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.12
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• pp.87-95
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• 2009

In this paper, an area-efficient FFT processor is proposed for MIMO-OFDM based SDR systems. The proposed scalable FFT processor can support the variable length of 64, 128, 512, 1024 and 2048. By reducing the required number of non-trivial multipliers with mixed-radix (MR) and multi-path delay commutator (MDC) architecture, the complexity of the proposed FFT processor is dramatically decreased without sacrificing system throughput The proposed FFT processor was designed in hardware description language (HDL) and synthesized to gate4eve1 circuits using 0.18um CMOS standard cell library. With the proposed architecture, the gate count for the processor is 46K and the size of memory is 64Kbits, which are reduced by 59% and 39%, respectively, compared with those of the 4-channel radix-2 single-path delay feedback (R2SDF) FFT processor. Also, compared with 4-channel radix-2 MDC (R2MDC) FFT processor, it is confirmed that the gate count and memory size are reduced by 16.4% and 26.8, respectively.