• 방송공학회논문지
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• 제28권1호
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• pp.149-152
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• 2023

본 논문에서는 소프트웨어 정의 라디오 (SDR: Software-defined Radio)를 활용하여 실시간 동영상 송수신기를 구현하기 위한 접근 방법을 제시한다. 이를 통해 최근 주목받고 있는 개방형 무선 접속망(O-RAN: Open Radio Access Network)을 연구하고 이를 SDR 장치와 개방형 소프트웨어를 통해 구현하고자 하는 연구자들의 접근 문턱을 낮추고 새로운 시각과 통찰력을 제공할 수 있을 것으로 기대한다.

• Journal of Communications and Networks
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• 제4권4호
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• pp.344-350
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• 2002

This work summarizes the current state of the art in software radio for 4G systems. Specifically, this work demonstrates that classic radio structures, e.g., heterodyne reception, homodyne reception, and their improved implementations, are inadequate selections for multi-mode reception. This opens the door to software defined radio, a novel reception architecture which promises ease in multi-band, multi-protocol design. The work presents the many advantages of such an architecture, including flexibility, reduced cost via component reduction, and improved reliability via, e.g., the elimination of environmental instability. The work also explains the limitations that currently curtail the widespread use of SDR, including issues surrounding A/D converters, management of software and power, and clock generation. This provides direction for future research to enable the broad applicability of SDR in 4G cellular and beyond.

• IEIE Transactions on Smart Processing and Computing
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• 제5권2호
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• pp.100-106
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• 2016

Spectrum sensing is an integral part of cognitive radio, which seeks to address the perceived spectrum scarcity that is caused by inefficient utilization of the available spectrum. In this paper, a spectrum sensing system using energy detection for analog TV and FM broadcast transmitters as well as modified Integrated Services Digital Broadcasting Terrestrial (ISDB-T) signals is implemented on a software-defined radio platform using GNU' Not Unix (GNU) radio and the N200 Universal Software Radio Peripheral (USRP). Real-time implementation and experimental tests were conducted in Metro Cebu, a highly urbanized area in the southern part of the Philippines. Extensive tests and measurements were necessary to determine spectrum availability, particularly in the TV band. This is in support of the Philippine government' efforts to provide internet connectivity to rural areas. Experimental results have so far met IEEE 802.22 requirements for energy detection spectrum sensing. The designed system detected signals at -114 dBm within a sensing time of 100 ms. Furthermore, the required $P_d({\geq}90)$ and $P_{fa}({\leq}10)$ of the standard were also achieved with different thresholds for various signal sources representing primary users.

• 한국산학기술학회논문지
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• 제9권3호
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• pp.674-680
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• 2008

범용 컴퓨팅 기반 SDR (Software Defined Radio) 시스템은 높은 개발 효율성, 소프트웨어 호환성, 범용 프로세서 사용에 따른 가격대비 성능의 혜택 등의 장점을 갖는다. 본 논문은 인텔 펜티엄 프로세서 및 리눅스로 운용되는 범용 컴퓨팅 플랫폼에서 동작하는 SDR 방식의 무선전화기 겸 워키토키 시스템의 설계 및 구현을 다룬다. 이를 위해 RF 전단부 하드웨어를 개발하여 오픈 소스로 진행 중인 GNU radio 미들웨어와 연동되도록 하였으며 그 위에 변조/복조 소프트웨어 모듈을 개발하였다. 실험 결과, 기존 900 MHz 상용 무선전화기와 호환되며 동시에 FM 워키토키를 지원하는 범용 컴퓨팅 플랫폼 기반 SDR 소프트웨어를 성공적으로 운용할 수 있음을 확인할 수 있었다. 그러나 런타임 소프트웨어 재구성 지원, TCP/IP통신 프로토콜과의 효율적인 연동 등은 향후 개선을 위한 연구가 이루어져야 할 것으로 파악되었다.

• 디지털산업정보학회논문지
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• 제15권4호
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• pp.93-101
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• 2019

This paper presents a software design and implementation of software-defined radio based IEEE 802.11ac encoder using Texas Instruments TMS320C6670 digital signal processor (DSP) platform. In this paper, the implemented encoder has the capability of generating all the signals consisting of preamble field and data field under different modulation & coding scheme in the IEEE 802.11ac standard. Moreover, the flexibility in choosing different rate, bandwidth, or mode can also be achieved by software reconfiguration using the DSP. As a result, by utilizing the computing power provided by multi-cores as well as the FFT coprocessors in the DSP, the required maximum throughput 78Mbps can be fully reached within 4 ㎲ for each OFDM symbol in the case of 20MHz bandwidth of IEEE 802.11ac.

• Journal of Information Processing Systems
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• 제8권1호
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• pp.133-144
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• 2012

In order to make cognitive radio systems a practical technology to be deployed in real-world scenarios, the core Software Defined Radio (SDR) systems must meet the stringent requirements of the target application, especially in terms of performance and energy consumption for mobile platforms. In this paper we present a feasibility study of hardware acceleration as an energy-efficient implementation for SDR. We identified the amplifier function from the Software Communication Architecture (SCA) for hardware acceleration since it is one of the functions called for most frequently and it requires intensive floating-point computation. Then, we used the Virtex5 Field-Programmable Gate Array (FPGA) to perform a comparison between compiler floating-point support and the on-chip floating-point support. By enabling the on-chip floating-point unit (FPU), we obtained as high as a 2X speedup and 50% of the overall energy reduction. We achieved this with an increase of the power consumption by no more than 0.68%. This demonstrates the feasibility of the proposed approach.

• 한국정보과학회:학술대회논문집
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• 한국정보과학회 2003년도 가을 학술발표논문집 Vol.30 No.2 (1)
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• pp.355-357
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• 2003

최근 급속한 발전으로 인해 다양해지고 있는 무선 통신 기술들은 각자의 고유한 주파수, 채널 부호화 기법. 변복조 기법을 쓰는 경우가 많다. 이로 인해, 다양한 무선 통신 기술간의 비호환성 문제가 제기되고 있다. 이러한 문제를 해결하기 위한 기술이 SDR(Software Defined Radio)이다. SDR은 신호 처리(Signal Processing)를 소프트웨어적으로 구현하는 것이다. 이러한 SDR 기술은 하나의 하드웨어를 이용해서 설러 무선 통신 기술들을 이용할 수 있게 한다. 현재 대부분의 SDR의 연구는 재구성 가능한 하드웨어 로직과 코어 프레임워크인 SCA(Software Communication Architecture)로 초점이 맞추어지고 있다 하지만 SDR 시스템의 특성을 고려했을 때, 실시간성(Real-Time)과 유연성(Flexibility), 재구성(Reconfigurability)을 위한 기능을 추가하기 위해 이에 적합한 운영체제의 연구가 필요하다. 본 논문에서는 휴대 기기에서의 SDR 시스템에 대해 간략히 알아보고 이를 위한 운영체제의 요구사항을 설명하여 그에 적합한 운영체제의 구조와 재구성 기법을 설명한다.

• 한국산업정보학회논문지
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• 제17권2호
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• pp.11-18
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• 2012

Smart Dynamic Pricing has been introduced to address the under-utilised network resources problem in mobile telecommunications systems. In this paper, we investigate the applicability of Smart Dynamic Pricing and its signalling models into Cognitive Radio Systems. Cognitive Radio System is defined as one in which cognitive radios are employed to access shared spectrum and/or dynamically allocated spectrum. Network elements, protocols, traffic and control channels, and system architecture are proposed for the implementation of Smart Dynamic Pricing in Cognitive Radio System. It is found that Smart Dynamic Pricing and its signalling models can be applied to Cognitive Radio Systems.

• ETRI Journal
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• 제35권5호
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• pp.767-774
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• 2013

In this paper, a novel parallel Viterbi decoding scheme is proposed to decrease the decoding latency and power consumption for the software-defined radio (SDR) system. It implements a divide-and-conquer approach by first dividing a block into a series of subblocks, then performing independent Viterbi decoding for each subsequence, and finally merging the surviving subpaths into the final path. Moreover, a network-on-chip-based SDR platform is used to evaluate the performance of the proposed parallel Viterbi decoding scheme. The experiment results show that our scheme can speed up the Viterbi decoding process without increasing the BER, and it performs better than the current state-of-the-art methods.

• ETRI Journal
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• 제30권1호
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• pp.113-128
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• 2008

Turbo codes are extensively used in current communications standards and have a promising outlook for future generations. The advantages of software defined radio, especially dynamic reconfiguration, make it very attractive in this multi-standard scenario. However, the complex and power consuming implementation of the maximum a posteriori (MAP) algorithm, employed by turbo decoders, sets hurdles to this goal. This work introduces an ASIP architecture for the MAP algorithm, based on a dual-clustered VLIW processor. It displays the good performance of application specific designs along with the versatility of processors, which makes it compliant with leading edge standards. The machine deals with multi-operand instructions in an innovative way, the fetching and assertion of data is serialized and the addressing is automatized and transparent for the programmer. The performance-area trade-off of the proposed architecture achieves a throughput of 8 cycles per symbol with very low power dissipation.