• Title/Summary/Keyword: basic research

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Recent Progress in Organic Thin Film Transistor on the Plastic Substrates

  • Suh, Kyung-Soo;Kang, Seung-Youl;Ahn, Seong-Deok;Oh, Ji-Young;You, In-Kyu;Kim, Gi-Hyun;Baek, Kyu-Ha;Kim, Chul-Am;Hwang, Chi-Sun;KoPark, Sang-Hee;Yang, Yong-Suk;Chung, Sung-Mook;Lee, Jeong-Ik;Do, Lee-Mi;Chu, Hye-Yong;Kang, Kwang-Yong
    • 한국정보디스플레이학회:학술대회논문집
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    • 2005.07a
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    • pp.61-63
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    • 2005
  • Pentacene based OTFT on PC and PES plastic substrates have been fabricated in a scale of 5 inches. We could get a small OTFT device enough to be applicable for AMOLED by acquiring the at least misalignment margin through a contact aligner. And also we could find out the degradation of device parameter through the integration processes and improve the properties by using a buffer layer as an etch stopper in an active patterning. Through these, the mobility of device is more than about $0.2cm^2/Vs$ and $I_{on}/I_{off}$ is higher than $10^5$.

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A Novel Process for Fabricating High Density Trench MOSFETs for DC-DC Converters

  • Kim, Jong-Dae;Roh, Tae-Moon;Kim, Sang-Gi;Park, Il-Yong;Yang, Yil-Sulk;Lee, Dae-Woo;Koo, Jin-Gun;Cho, Kyoung-Ik;Kang, Young-Il
    • ETRI Journal
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    • v.24 no.5
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    • pp.333-340
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    • 2002
  • We propose a new process technique for fabricating very high-density trench MOSFETs using 3 mask layers with oxide spacers and a self-aligned technique. This technique reduces the device size in trench width, source, and p-body region with a resulting increase in cell density and current driving capability as well as cost-effective production capability. We were able to obtain a higher breakdown voltage with uniform oxide grown along the trench surface. The channel density of the trench DMOSFET with a cell pitch of 2.3-2.4 ${\mu}m$ was 100 Mcell/$in^2$ and a specific on-resistance of 0.41 $m{\Omega}{\cdot}cm^2$ was obtained under a blocking voltage of 43 V.

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Fabrication of Thin Film Transistor on PES substrate using Sequential Lateral Solidification Crystallized Poly-Si Films

  • Kim, Yong-Hae;Chung, Choong-Heui;Yun, Sun-Jin;Park, Dong-Jin;Kim, Dae-Won;Lim, Jung-Wook;Song, Yoon-Ho;Moon, Jae-Hyun;Lee, Jin-Ho
    • 한국정보디스플레이학회:학술대회논문집
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    • 2005.07a
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    • pp.269-271
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    • 2005
  • Using optimized sputtering condition of a-Si and $SiO_2$ thin film, we can obtained the large grained poly-Si film on PES substrate. The gate dielectric grown by plasma enhanced atomic layer deposition, laser activation and organic interlayer dielectric material make TFTs on PES possible with mobility of $11cm^2/Vs$ (nMOS) and $7cm_2/Vs$ (pMOS).

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Dielectric Properties of Poly(vinyl phenol)/Titanium Oxide Nanocomposite Thin Films formed by Sol-gel Process

  • Myoung, Hey-J;Kim, Chul-A;You, In-Kyu;Kang, Seung-Y;Ahn, Seong-D;Kim, Gi-H;Oh, ji-young;Baek, Kyu-Ha;Suh, Kyung-S;Chin, In-Joo
    • 한국정보디스플레이학회:학술대회논문집
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    • 2005.07b
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    • pp.1572-1575
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    • 2005
  • Poly(vinyl phenol)(PVP)/$TiO_2$ nanocomposite the films have been prepared incorporating metal alkoxide with vinyl polymer to obtain high dielectric constant gate insulating material for a organic thin film transistor. The surface composition, the morphology, and the thermal and electrical properties of the hybrid nanocomposite films were observed by ESCA, scanning electron microscopy (SEM), atomic force microscopy(AFM), and thermogravimetric analysis (TGA). Thin hybrid films exhibit much higher dielectric constants (7.79 at 40wt% metal alkoxide).

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Characteristics of Surface Roughness as a Film Thickness and Planarization of SLS Poly-Si Films

  • Sohn, Choong-Yong;Kim, Yong-Hae;Ko, Young-Wook;Chung, Choong-Heui;Hwang, Chi-Sun;Song, Yoon-Song;Lee, Jin-Ho
    • 한국정보디스플레이학회:학술대회논문집
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    • 2003.07a
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    • pp.683-685
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    • 2003
  • We report on a surface planarization process that produces more planar surface than previous sequential lateral solidification crystallized poly silicon films. By applying the single shot laser irradiation with optimum energy density ($(817mJ/cm^{2})$ on the ridge area after SLS crystallization, the ridge height can be decreased.

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A Serial Input/Output Circuit with 8 bit and 16 bit Selection Modes

  • Yang, Yil-Suk;Kim, Jong-Dae;Roh, Tae-Moon;Lee, Dae-Woo;Koo, Jin-Gun;Kim, Sang-Gi;Park, Il-Yong;Yu, Byoung-Gon
    • ETRI Journal
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    • v.24 no.6
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    • pp.462-464
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    • 2002
  • This paper presents a serial interface circuit that permits selection of the amount of data converted from serial-to-parallel and parallel-to-serial and overcomes the disadvantages of the conventional serial input/output interface. Based on the selected data length operating mode, 8 bit or 16 bit serial-to-parallel and 8 bit or 16 bit parallel-to-serial conversion takes place in data blocks of the selected data length.

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