• Journal of Information Processing Systems
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• v.10 no.3
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• pp.429-442
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• 2014

In this paper, we investigated the use of seasonal autoregressive integrated moving average (SARIMA) time series models for fault detection in semiconductor etch equipment data. The derivative dynamic time warping algorithm was employed for the synchronization of data. The models were generated using a set of data from healthy runs, and the established models were compared with the experimental runs to find the faulty runs. It has been shown that the SARIMA modeling for this data can detect faults in the etch tool data from the semiconductor industry with an accuracy of 80% and 90% using the parameter-wise error computation and the step-wise error computation, respectively. We found that SARIMA is useful to detect incipient faults in semiconductor fabrication.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.3
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• pp.176-186
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• 1996

As the density of VLSI increases, the conventional logic testing is not sufficient to completely detect the new faults generated in design and fabrication processing. Recently, IDDQ testing becomes very attractive since it can overcome the limitations of logic testing. In this paper, G-ATPG (gyeongsang automatic test pattern genrator) is designed which is able to be adapted to IDDQ testing for combinational CMOS VLSI. In G-ATPG, stuck-at, transistor stuck-on, GOS (gate oxide short)or bridging faults which can occur within priitive gate or XOR is modelled to primitive fault patterns and the concept of a fault-sensitizing gate is used to simulate only gates that need to sensitize the faulty gate because IDDQ test does not require the process of fault propagation. Primitive fault patterns are graded to reduce CPU time for the gates in a circuit whenever a test pattern is generated. the simulation results in bench mark circuits show that CPU time and fault coverage are enhanced more than the conventional ATPG using IDDQ test.

• Structural Engineering and Mechanics
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• v.62 no.5
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• pp.567-576
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• 2017

Structural failures are undesirable events that devastate the construction industry resulting in loss of life, injury, huge property loss, and also affect the economy of the region. Roof truss failures occur mainly due to excessive loading, improper fabrication, deterioration, inadequate repair, etc. Although very rare, a roof truss may even fail due to inappropriate location of supports. One such case was reported from the recent failure of a steel roof truss used in an indoor stadium at Kargil in India. Kargil region, being mountainous in nature, receives heavy snowfall and hence the steel roof trusses are designed for heavy snow loads. Due to inappropriate support location, the indoor stadium's steel roof truss had failed under heavy snow load for which it was designed and became an interesting structural engineering problem. The failure observed was primarily in terms of yielding of the bottom chord under the supports, leading to partial collapse of the roof truss. This paper summarizes the results of laboratory tests and analytical studies that focused on the validation of the proposed remedial measure for rehabilitating this distressed steel roof truss. The study presents the evaluation of (i) significant reduction in strength and stiffness of the distressed truss resulting in its failure, (ii) desired recovery in both strength and stiffness of the rectified truss contributed by the proposed remedial measure. Three types of models i.e., ideal truss model, as build truss model and rectified truss model were fabricated and tested under monotonic loading. The structural configuration and support condition varied in all the three models to represent the ideal truss, distressed truss and the rectified truss. To verify the accuracy of the experimental results, an analytical study was carried out and the results of this analytical study are compared with the experimental ones.

• The Korean Journal of Applied Statistics
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• v.35 no.3
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• pp.407-419
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• 2022

The semiconductor fabrication process is complex and time-consuming. There are sometimes errors in the process, which results in defective die on the wafer bin map (WBM). We can detect the faulty WBM by finding some patterns caused by dies. When one manually seeks the failure on WBM, it takes a long time due to the enormous number of WBMs. We suggest a two-step approach to discover the probable pattern on the WBMs in this paper. The first step is to separate the normal WBMs from the defective WBMs. We adapt a hierarchical clustering for de-noising, which nicely performs this work by wisely tuning the number of minimum points and the cutting height. Once declared as a faulty WBM, then it moves to the next step. In the second step, we classify the patterns among the defective WBMs. For this purpose, we extract features from the WBM. Then machine learning algorithm classifies the pattern. We use a real WBM data set (WM-811K) released by Taiwan semiconductor manufacturing company.