The Journal of Korea Institute of Information, Electronics, and Communication Technology (한국정보전자통신기술학회논문지)

Korea Information Electronic Communication Technology (한국정보전자통신기술학회)
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New Thyristor Based ESD Protection Devices with High Holding Voltages for On-Chip ESD Protection Circuits

  • Received : 2019.04.12
  • Accepted : 2019.04.18
  • Published : 2019.04.30
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Abstract

In the design of semiconductor integrated circuits, ESD is one of the important issues related to product quality improvement and reliability. In particular, as the process progresses and the thickness of the gate oxide film decreases, ESD is recognized as an important problem of integrated circuit design. Many ESD protection circuits have been studied to solve such ESD problems. In addition, the proposed device can modify the existing SCR structure without adding external circuit to effectively protect the gate oxide of the internal circuit by low trigger voltage, and prevent the undesired latch-up phenomenon in the steady state with high holding voltage. In this paper, SCR-based novel ESD(Electro-Static Discharge) device with the high holding voltage has been proposed. The proposed device has the lower triggering voltage without an external trigger circuitry and the high holding voltage to prevent latch-up phenomenon during the normal condition. Using TCAD simulation results, not only the design factors that influence the holding voltage, but also comparison of conventional ESD protection device(ggNMOS, SCR), are explained. The proposed device was fabricated using 0.35um BCD process and was measured electrical characteristic and robustness. In the result, the proposed device has triggering voltage of 13.1V and holding voltage of 11.4V and HBM 5kV, MM 250V ESD robustness.

Keywords

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Fig. 1. Cross section of the proposed device and equivalent circuit

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Fig. 3. DC-IV characteristics of proposed device according to design variables (D1, D2, D3, D4)

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Fig. 2. (A) DC I-V characteristics with existing devices, (B) Voltage and temperature characteristics at HBM 4K

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Fig. 4. TLP-IV characteristics of proposed device according to design variables (D1, D2, D3, D4)

Table 1. Characteristics of proposed ESD protection device

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References

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