Journal of the Semiconductor & Display Technology (반도체디스플레이기술학회지)

The Korean Society Of Semiconductor & Display Technology (한국반도체디스플레이기술학회)
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A Study on Direct Cache-to-Cache Transfer for Hybrid Cache Architecture to Reduce Write Operations

쓰기 횟수 감소를 위한 하이브리드 캐시 구조에서의 캐시간 직접 전송 기법에 대한 연구

  • Juhee Choi (Dept. of Smart Information Communication Engineering, Sangmyung University)
  • 최주희 (상명대학교 스마트정보통신공학과)
  • Received : 2024.02.14
  • Accepted : 2024.03.20
  • Published : 2024.03.31
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Abstract

Direct cache-to-cache transfer has been studied to reduce the latency and bandwidth consumption related to the shared data in multiprocessor system. Even though these studies lead to meaningful results, they assume that caches consist of SRAM. For example, if the system employs the non-volatile memory, the one of the most important parts to consider is to decrease the number of write operations. This paper proposes a hybrid write avoidance cache coherence protocol that considers the hybrid cache architecture. A new state is added to finely control what is stored in the non-volatile memory area, and experimental results showed that the number of writes was reduced by about 36% compared to the existing schemes.

Keywords

Acknowledgement

본 연구는 2021년도 과학기술정보통신부의 재원으로 한국연구재단의 지원을 받은 기초연구사업 연구임(NRF2021R1G1A1004340).

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